74AUP1G374GF,132 NXP Semiconductors, 74AUP1G374GF,132 Datasheet - Page 13

• Manufacturer Part Number: 74AUP1G374GF,132
• Description: IC F-F D-TYPE POS EDGE 6-XSON
• Manufacturer: NXP Semiconductors
• Series: 74AUPr
• Type: D-Typer

Specifications of 74AUP1G374GF,132

• Output Type: Tri-State Non Inverted
• Package / Case: 6-XSON, SOT891
• Function: Standard
• Number Of Elements: 1
• Number Of Bits Per Element: 1
• Frequency - Clock: 53MHz
• Delay Time - Propagation: 23.6ns
• Trigger Type: Positive Edge
• Current - Output High, Low: 4mA, 4mA
• Voltage - Supply: 0.8 V ~ 3.6 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Number Of Circuits: 1
• Logic Family: AUP
• Logic Type: CMOS
• Polarity: Non-Inverting
• Input Type: Single-Ended
• Propagation Delay Time: 20.5 ns
• High Level Output Current: - 4 mA
• Low Level Output Current: 4 mA
• Supply Voltage (max): 3.6 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Supply Voltage (min): 0.8 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 74AUP1G374GF-H; 74AUP1G374GF-H; 935281333132

NXP Semiconductors
12. Waveforms
Table 9.
74AUP1G374
Product data sheet
Supply voltage Input
V
0.8 V to 1.6 V
1.65 V to 2.7 V
3.0 V to 3.6 V
Fig 7.
CC
Measurement points are given in
The shaded areas indicate when the input is permitted to change for predictable output performance.
Logic levels: V
The clock input (CP) to output (Q) propagation delays, clock input (CP) pulse width, data input (D) to
clock input (CP) set-up times, clock input (CP) to data input (D) hold times and the maximum frequency
(CP)
Measurement points
V
0.5  V
0.5  V
0.5  V
M
OL
CC
CC
CC
and V
CP input
Q output
D input
OH
are typical output voltage levels that occur with the output load.
V
V
V
V
GND
GND
V
V
I
CC
CC
CC
OH
OL
V
V
I
I
Table
All information provided in this document is subject to legal disclaimers.
9.
V
M
t
su(L)
Rev. 5 — 14 July 2010
t
 3.0 ns
 3.0 ns
 3.0 ns
r
= t
Low-power D-type flip-flop; positive-edge trigger; 3-state
t
V
f
h
M
V
t
W
M
t
PHL
1/f
clk
Output
V
0.5  V
0.5  V
0.5  V
M
t
su(H)
CC
CC
CC
t
h
001aad498
V
V
V
V
t
PLH
X
OL
OL
OL
74AUP1G374
+ 0.1 V
+ 0.15 V
+ 0.3 V
© NXP B.V. 2010. All rights reserved.
V
V
V
V
Y
OH
OH
OH
 0.1 V
 0.15 V
 0.3 V
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