rs5c62 RICOH Co.,Ltd., rs5c62 Datasheet - Page 26

• Manufacturer Part Number: rs5c62
• Description: Real-time Clock
• Manufacturer: RICOH Co.,Ltd.

22
RP/RF/RS5C62
5. Interrupts
1) Alarm interrupt: Requested upon driving low (turning on) the INTR pin in matching between preset alarm time
2) Cyclic interrupt: Requested upon driving low (turning on) the INTR pin with a preset cycle.
Interrupt Registers
5.1 Alarm Interrupt
bit set to “0” and then to “1” in the control register 1. Upon matching between the preset alarm time and the time
indicated by the time counter, the INTR pin is driven low (turned on) to output a request for an alarm interrupt.
The INTR pin output can be controlled by using the ALEN bit in the control register 1 and the ALFG bit in the con-
trol register 2.
*
*
*
*
*
Alarm-time ................ Alarm register
Cyclic ....................... Cyclic interrupt select register
Interrupts are available in the following two types:
Desired alarm time (in minutes and hours) can be preset in the alarm digits of the alarm register with the ALEN
(in minutes and hours) and time indicated by the time counter (in minutes and hours).
To output an alarm interrupt and a cyclic interrupt, the INTR pin is configured as shown in the figure below:
1) When an alarm interrupt and a cyclic interrupt are generated in combination, their logical sum (OR) is output from the INTR pin. In this event, they
2) The INTR pin output has indefinite states at power-on from 0V.
3) An alarm interrupt and a cyclic interrupt are both enabled whether the CE pin input is held high or low.
1) The above figure assumes that an alarm interrupt occurs in the absence of a cyclic interrupt.
2) The ALFG bit has an inverse logic from that of the INTR pin output.
can be distinguished from each other by reading the ALFG and CTFG bits of the control register 2.
INTR
INTR
ALEN bi
ALFG bit
CTFG bit
ALEN=1
ALEN=1
Cyclic interrupt
Alarm interrupt
Alarm time match
Alarm time match
Alarm time match period: 1 minute
MAX.61.1µs
ALFG=0
ALEN=0
ALEN=1
(See “2. 6 Alarm Register”.)
(See “2. 1 Control Register 1”.)
(See “2. 2 Control Register 2”.)
(See “2. 5 Control Register 2”.)
(See “2. 2 Control Register 2”.)
ALEN=0
INTR
Alarm time match
Alarm time match