ds265188-port-t1-e1-j1-transc Maxim Integrated Products, Inc., ds265188-port-t1-e1-j1-transc Datasheet - Page 5

• Manufacturer Part Number: ds265188-port-t1-e1-j1-transc
• Description: Ds26518 8-port T1/e1/j1 Transceiver
• Manufacturer: Maxim Integrated Products, Inc.

DS26518 8-Port T1/E1/J1 Transceiver
LIST OF FIGURES
Figure 7-1. Block Diagram ......................................................................................................................................... 18
Figure 7-2. Detailed Block Diagram........................................................................................................................... 19
Figure 8-1. BGA Pinout.............................................................................................................................................. 28
Figure 9-1. SPI Serial Port Access for Read Mode, SPI_CPOL = 0, SPI_CPHA = 0 ............................................... 30
Figure 9-2. SPI Serial Port Access for Read Mode, SPI_CPOL = 1, SPI_CPHA = 0 ............................................... 30
Figure 9-3. SPI Serial Port Access for Read Mode, SPI_CPOL = 0, SPI_CPHA = 1 ............................................... 30
Figure 9-4. SPI Serial Port Access for Read Mode, SPI_CPOL = 1, SPI_CPHA = 1 ............................................... 30
Figure 9-5. SPI Serial Port Access for Write Mode, SPI_CPOL = 0, SPI_CPHA = 0 ............................................... 31
Figure 9-6. SPI Serial Port Access for Write Mode, SPI_CPOL = 1, SPI_CPHA = 0 ............................................... 31
Figure 9-7. SPI Serial Port Access for Write Mode, SPI_CPOL = 0, SPI_CPHA = 1 ............................................... 31
Figure 9-8. SPI Serial Port Access for Write Mode, SPI_CPOL = 1, SPI_CPHA = 1 ............................................... 31
Figure 9-9. Backplane Clock Generation................................................................................................................... 32
Figure 9-10. Device Interrupt Information Flow Diagram........................................................................................... 36
Figure 9-11. IBO Multiplexer Equivalent Circuit—4.096MHz .................................................................................... 41
Figure 9-12. IBO Multiplexer Equivalent Circuit—8.192MHz .................................................................................... 42
Figure 9-13. IBO Multiplexer Equivalent Circuit—16.384MHz .................................................................................. 43
Figure 9-14. RSYNCn Input in H.100 (CT Bus) Mode............................................................................................... 47
Figure 9-15. TSSYNCIOn (Input Mode) Input in H.100 (CT Bus) Mode ................................................................... 47
Figure 9-16. CRC-4 Recalculate Method .................................................................................................................. 71
Figure 9-17. Receive HDLC-64 Message Example................................................................................................... 78
Figure 9-18. Transmit HDLC-64 Message Example.................................................................................................. 80
Figure 9-19. Receive HDLC-256 Message Example................................................................................................. 83
Figure 9-20. Transmit HDLC-256 Message Example................................................................................................ 84
Figure 9-21. Network Connection—Longitudinal Protection ..................................................................................... 87
Figure 9-22. T1/J1 Transmit Pulse Templates .......................................................................................................... 90
Figure 9-23. E1 Transmit Pulse Templates ............................................................................................................... 91
Figure 9-24. Receive LIU Termination Options ......................................................................................................... 93
Figure 9-25. Typical Monitor Application ................................................................................................................... 94
Figure 9-26. HPS Block Diagram............................................................................................................................... 96
Figure 9-27. Jitter Attenuation ................................................................................................................................... 97
Figure 9-28. Loopback Diagram ................................................................................................................................ 98
Figure 9-29. Analog Loopback................................................................................................................................... 98
Figure 9-30. Local Loopback ..................................................................................................................................... 99
Figure 9-31. Remote Loopback 2 .............................................................................................................................. 99
Figure 9-32. Dual Loopback .................................................................................................................................... 100
Figure 11-1. T1 Receive-Side D4 Timing ................................................................................................................ 273
Figure 11-2. T1 Receive-Side ESF Timing.............................................................................................................. 273
Figure 11-3. T1 Receive-Side Boundary Timing (Elastic Store Disabled)............................................................... 274
Figure 11-4. T1 Receive-Side 1.544MHz Boundary Timing (Elastic Store Enabled).............................................. 274
Figure 11-5. T1 Receive-Side 2.048MHz Boundary Timing (Elastic Store Enabled).............................................. 275
Figure 11-6. T1 Receive-Side Interleave Bus Operation—BYTE Mode.................................................................. 276
Figure 11-7. T1 Receive-Side Interleave Bus Operation—FRAME Mode .............................................................. 277
Figure 11-8. T1 Receive-Side RCHCLKn Gapped Mode During F-Bit.................................................................... 277
Figure 11-9. T1 Transmit-Side D4 Timing ............................................................................................................... 278
Figure 11-10. T1 Transmit-Side ESF Timing........................................................................................................... 278
Figure 11-11. T1 Transmit-Side Boundary Timing (Elastic Store Disabled)............................................................ 279
Figure 11-12. T1 Transmit-Side 1.544MHz Boundary Timing (Elastic Store Enabled)........................................... 279
Figure 11-13. T1 Transmit-Side 2.048MHz Boundary Timing (Elastic Store Enabled)........................................... 280
Figure 11-14. T1 Transmit-Side Interleave Bus Operation—BYTE Mode............................................................... 281
5 of 313