ds265188-port-t1-e1-j1-transc Maxim Integrated Products, Inc., ds265188-port-t1-e1-j1-transc Datasheet - Page 262

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ds265188-port-t1-e1-j1-transc

Manufacturer Part Number
ds265188-port-t1-e1-j1-transc
Description
Ds26518 8-port T1/e1/j1 Transceiver
Manufacturer
Maxim Integrated Products, Inc.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Note: All latched bits in this register can create interrupts.
Bit 2: BERT Bit Error Detected Event (BED). A latched bit that is set when a bit error is detected. The receive
BERT must be in synchronization for it to detect bit errors.
Bit 1: BERT Bit Counter Overflow Event (BBCO). A latched bit that is set when the 32-bit BERT bit counter
(BBC) overflows.
Bit 0: BERT Error Counter Overflow Event (BECO). A latched bit that is set when the 24-bit BERT error counter
(BEC) overflows.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit 2: Bit Error Detected Event (BED)
Bit 1: BERT Bit Counter Overflow Event (BBCO)
Bit 0: BERT Error Counter Overflow Event (BECO)
0 = interrupt masked
1 = interrupt enabled
0 = interrupt masked
1 = interrupt enabled
0 = interrupt masked
1 = interrupt enabled
7
0
7
0
BLSR2
BERT Latched Status Register 2
1404h + (10h x (n - 1)) : where n = 1 to 8
BSIM2
BERT Status Interrupt Mask Register 2
1405h + (10h x (n - 1)) : where n = 1 to 8
6
0
6
0
5
0
5
0
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4
0
4
0
3
0
3
0
DS26518 8-Port T1/E1/J1 Transceiver
BED
BED
2
0
2
0
BBCO
BBCO
1
0
1
0
BECO
BECO
0
0
0
0

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