cy2212 Cypress Semiconductor Corporation., cy2212 Datasheet - Page 4

• Manufacturer Part Number: cy2212
• Description: Clock Generator Lite
• Manufacturer: Cypress Semiconductor Corporation.

Document #: 38-07466 Rev. *A
AC Device Specifications
Functional Specifications
This section gives the detailed functional specifications of the
device physical layer. These specifications refer to the logical
and physical interfaces.
Crystal Input
The CY2212 receives its reference from an external crystal.
Pin XIN is the reference crystal input, and pin XOUT is the
reference crystal feedback. The parameters for the crystal are
given on page 3 of this data sheet.
Select Input
There is only one select input, pin S. This pin selects the
frequency multiplier in the PLL, and is a standard LVCMOS
input. The S pin has an internal pull-up resistor. The multiplier
selection is given on page 1 of this data sheet.
LCLK Output Driver
In addition to the Rambus clock driver outputs, there is another
clock output driver. The LCLK driver is a standard LVCMOS
output driver. Figure 1 below shows the LCLK output driver
load circuit.
Notes:
t
t
BW
t
t
t
t
DC
10. LCLK cycle jitter and 10-cycle jitter are defined as the difference between the measured period and the nominal period as defined on page 8.
11. LCLK 10-cycle jitter specification is based on the measured value of LCLK cycle jitter as defined on page 8.
CR
CR, CF
CYCLE,L
LR
JC,L
J10,L
Parameter
, t
, t
L
LOOP
LF
CF
Figure 1. LCLK Test Load Circuit
LCLK
Output rise and fall times (measured at 20%–80% of output voltage)
Difference between output rise and fall times on the same pin of a single
device (20%–80%)
PLL loop bandwidth
LCLK clock cycle time
LCLK output rise and fall time
LCLK cycle jitter
LCLK 10-cycle jitter
LCLK output duty cycle
10 pF
[10]
(continued)
120Ω
120Ω
[10,11]
Description
RSL Clock Output Driver
Figure 2 shows the clock driver equivalent circuit.
The differential driver has a low output impedance in the range
of about 20 ohms. The driver also produces a specified voltage
swing on the channel. The nominal value of the channel
impedance, Z
resistor RP are used to set the voltage swing on the channel.
The driver output characteristics are defined together with the
external components, and the output clock is specified at the
measurement point indicated in Figure 2. The complete set of
external components for the output driver, including edge-rate
filter capacitors required for system operation, are shown in
Figure 3. The values for the external components are given in
Table 1.
The output clocks drive transmission lines, potentially long
lines. Since circuit board traces will act as lossy, imperfectly
terminated transmission lines with some discontinuities, there
will be reflections generated which will travel back to the
DRCG-Lite output driver. If the output impedance does not
match ZCH, secondary reflections will be generated that will
add to position-dependent timing uncertainty. Therefore, the
CY2212 not only provides proper output voltage swings, but
also provides a well-matched output impedance. The driver
impedance, R
in parallel with R
The clock driver is specified as a black-box at the packaged
pins. The output characteristics are measured after the series
resistance, R
no applied termination voltage.
Differential
Driver
S
CH
OUT
. The outputs are terminated differentially, with
Figure 2. Equivalent Circuit
, is 28 ohms. Series resistor RS and parallel
P
, is in series with R
.
R
R
R
S
S
S
–1.1 * t
(–3 dB)
50 kHz
106.6
R
40%
Min.
–0.8
R
250
Measurement Point
Measurement Point
P
–
–
P
JC,L
S
, and the combination is
1.1 * t
Z
(–20 dB)
Z
8 MHz
CH
142.2
CH
Max.
60%
500
100
0.8
1
JC,L
CY2212
Page 4 of 10
R
R
T
T
t
= Z
= Z
CYCLE,L
Unit
ps
ps
ns
ns
ns
ns
CH
CH
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