cy2212 Cypress Semiconductor Corporation., cy2212 Datasheet - Page 3

• Manufacturer Part Number: cy2212
• Description: Clock Generator Lite
• Manufacturer: Cypress Semiconductor Corporation.

Document #: 38-07466 Rev. *A
DC Electrical Specifications
AC Electrical Specifications
DC Device Specifications
State Transition Characteristics
Specifies the maximum settling time of the CLK, CLKB, and
LCLK outputs from device power-up. For V
any sequences are allowed to power-up and power-down the
CY2212 DRCG-Lite.
AC Device Specifications
V
V
T
V
V
R
f
C
C
V
V
V
V
V
r
V
V
V
t
t
t
DC
t
Notes:
XTAL,IN
CYCLE
J
JL
DC,ERR
OUT
5. Nominal condition with 18.75-MHz crystal.
6. Capacitance measured at Freq = 1 MHz, DC Bias = 0.9 V, and VAC < 100 mV.
7. V
8. r
9. Output short-term jitter specification is peak-peak and defined in Figure 10.
A
DD
DDL
IL
IH
CM
X
COS
COH
COL
LOH
LOL
DD
PUP
IN,CMOS
XTAL
Parameter
Parameter
Parameter
Parameter
OUT
/V
COS
DDL
= ∆ V
From
= V
/V
OH
O
DDP
/ ∆ I
– V
O
OL
On CLK/CLKB/LCLK Normal
. This is defined at the output pins, not at the measurement point of Figure 3.
Clock cycle time
Jitter over 1–6 clock cycles at 400 MHz
Jitter over 1–6 clock cycles at 300 MHz
Long-term jitter at 400 MHz
Long-term jitter at 300 MHz
Long-term average output duty cycle
Cycle-cycle duty cycle error at 400 MHz
Cycle-cycle duty cycle error at 300 MHz
.
Supply voltage
LCLK supply voltage
Ambient operating temperature
Input signal low voltage at pin S
Input signal high voltage at pin S
Internal pull-up resistance
Input frequency at crystal input
Input capacitance at S pin
Crystal load capacitance
Differential output common-mode voltage
Differential output crossing-point voltage
Output voltage swing (p-p single-ended)
Output high voltage
Output low voltage
Output dynamic resistance (at pins)
LCLK Output high voltage at I
LCLK Output low voltage at I
Description
To
Description
Description
DD
, V
[6]
DDP
OL
OH
Description
Transition Latency
[5]
, and V
= 10 mA
= –10 mA
[8]
[9]
[9]
3 ms
DDL
[7]
14.0625
Min.
–
–
V
DDL
Time from V
CLK/CLKB/LCLK outputs settled
Min.
3.04
0.65
Min.
1.35
1.25
1.7
0.4
1.0
10
12
– 0.45V
0
–
–
0
Typ.
11
–
–
DD
/V
DDL
/V
Description
Max.
Max.
V
DDP
3.56
0.35
1.75
1.85
0.45
100
2.1
0.7
2.1
70
50
DDL
–
–
Min.
45%
18.75
2.5
Max.
is applied and settled to
–
–
–
–
–
–
10
–
Max.
55%
3.33
100
140
300
400
50
70
CY2212
Page 3 of 10
Unit
V
V
Unit
kΩ
°C
MHz
Unit
Ω
V
V
V
V
V
V
V
V
V
DD
DD
pF
pF
t
CYCLE
Unit
ns
ps
ps
ps
ps
ps
ps
[+] Feedback