cy28325-3 Cypress Semiconductor Corporation., cy28325-3 Datasheet - Page 8

• Manufacturer Part Number: cy28325-3
• Description: Ftg For Via Pentium 4 Chipsets
• Manufacturer: Cypress Semiconductor Corporation.

Document #: 38-07590 Rev. *.*
Data Byte 3
Data Byte 4
Data Byte 5
Data Byte 6
Bit
Bit
Bit
Bit
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
Pin#
Pin#
Pin#
Pin#
10
27
26
23
45
46
8
7
8
–
–
–
–
–
–
–
–
7
8
–
–
1
–
–
–
SEL_48MHZ
48MHz
24_48MHz
PCI_F
AGP2
AGP1
AGP0
PCI_Skew1
PCI_Skew0
WD_TIMER4
WD_TIMER3
WD_TIMER2
WD_TIMER1
WD_TIMER0
WD_PRE_SCALER
48MHz_DRV
24_48MHz_DRV
APCI1
APIC0
SW_MULTSEL1
SW_MULTSEL0
REF
MULTSEL_Override This bit control the selection of IREF multipler.
Reserved
Reserved
Name
Name
Name
Name
48-MHz clock output drive strength
0 = Normal
1 = High Drive
0 = Normal
1 = High Drive
(Active/Inactive)
(Active/Inactive)
IREF multiplier
00 = Ioh is 4 × IREF
01 = Ioh is 5 × IREF
10 = Ioh is 6 × IREF
11 = Ioh is 7 × IREF
(Active/Inactive)
0 = HW control; IREF multiplier is determined by MULTSEL1 input pin
1 = SW control; IREF multiplier is determined by SW_MULTSEL[0:1]
24_48 MHz clock output drive strength
PCI skew control
00 = Normal
01 = –500 ps
10 = Reserved
11 = +500 ps
These bits store the time-out value of the Watchdog Timer. The scale
of the timer is determine by the prescaler. The timer can support a
value of 150 ms to 4.8 sec when the prescaler is set to 150 ms. If the
prescaler is set to 2.5 sec, it can support a value from 2.5 sec to 80
sec. When the Watchdog Timer reaches “0,” it will set the
WD_TO_STATUS bit and generate Reset if RST_EN_WD is enabled.
0 = 150 ms
1 = 2.5 sec
0 = 24 MHz
1 = 48 MHz
1 = Enabled, 0 = Disabled
1 = Enabled, 0 = Disabled
1 = Enabled, 0 = Disabled
1 = Enabled, 0 = Disabled
1 = Enabled, 0 = Disabled
1 = Enabled, 0 = Disabled
Reserved
Reserved
Pin Description
Pin Description
Pin Description
Pin Description
CY28325-3
Page 8 of 19
Power-on
Power-on
Power-on
Power-on
Default
Default
Default
Default
1
1
1
0
0
1
0
1
0
1
1
1
1
1
1
0
0
1
1
1
1
1
0
1
1
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