cy28325-3 Cypress Semiconductor Corporation., cy28325-3 Datasheet
cy28325-3
Related parts for cy28325-3
cy28325-3 Summary of contents
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... PCI3 PCI_F PCI4 VDD_PCI PCI1:8 PCI5 PCI6 PCI7 GND_PCI PCI8 *PD# AGP0 VDD_48MHz VDD_AGP 48MHz 24_48MHz RST# • 3901 North First Street • San Jose CY28325-3 PCI REF APIC 48M 24_48M [1] SSOP- VDD_APIC 2 47 GND_APIC 3 46 ...
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... SMBus Clock Input: Clock pin for serial interface. I/O SMBus Data Input: Data pin for serial interface. O System Reset Output: Open-drain system reset output. I Current Reference for CPU output: A precision resistor is attached to this pin, which is connected to the internal current reference. CY28325-3 Description Page [+] Feedback ...
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... CY28325-3 Description PLL Gear Constants PCI APIC (G) 34.0 17.0 48.00741 35.0 17.5 48.00741 36.0 18.0 48.00741 37.0 18.5 48.00741 38.0 19.0 48.00741 39.0 19.5 48.00741 40.0 20.0 48.00741 41.0 20.5 48.00741 31.5 18.0 48.00741 32.5 18.5 48.00741 34.0 17.0 48.00741 35.0 17.5 48.00741 36.0 18.0 48.00741 37.0 18.5 48.00741 38.0 19.0 48.00741 39.0 19.5 48.00741 40 ...
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... IREF = 2. 475 1 IREF = 2. 475 1 IREF = 2. 475 1 IREF = 2. 475 1 IREF = 2. 475 1 IREF = 2.32mA Rr = 475 1 IREF = 2.32mA CY28325-3 PLL Gear Constants APIC (G) 18.5 48.00741 19.0 48.00741 16.8 48.00741 16.7 48.00741 16.7 48.00741 16.7 48.00741 16.7 48.00741 16.7 48.00741 16.7 48.00741 16.7 48.00741 ...
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... Byte count from slave – 8 bits 38 Acknowledge from master 39:46 Data byte from slave – 8 bits 47 Acknowledge from master 48:55 Data byte from slave – 8 bits 56 Acknowledge from master .... Data byte N from slave – 8 bits .... Acknowledge from master .... Stop CY28325-3 Page [+] Feedback ...
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... Acknowledge from slave 20:27 Data byte from master – 8 bits 28 Acknowledge from slave 29 Stop Document #: 38-07590 Rev. *.* CY28325-3 Byte Read Protocol Bit Description 1 Start 2:8 Slave address – 7 bits 9 Write = 0 10 Acknowledge from slave 11:18 Command Code – ...
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... CPUT_CS_F and CPUC_CS_F are Free-running outputs 0 = CPUT_CS_F and CPUC_CS_F will be disabled when CPU_STOP# is active Pin Description 1 = Enabled Disabled 1 = Enabled Disabled 1 = Enabled Disabled 1 = Enabled Disabled 1 = Enabled Disabled 1 = Enabled Disabled 1 = Enabled Disabled 1 = Enabled Disabled Pin Description Reserved CY28325-3 Power-on Default Power-on Default 0 ...
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... Ioh is 4 × IREF 01 = Ioh is 5 × IREF 10 = Ioh is 6 × IREF 11 = Ioh is 7 × IREF (Active/Inactive control; IREF multiplier is determined by MULTSEL1 input pin control; IREF multiplier is determined by SW_MULTSEL[0:1] Pin Description Reserved Reserved CY28325-3 Power-on Default ...
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... Low Drive 1 = High Drive This bit will enable the generation of a Reset pulse when a Watchdog timer time-out occurs Disabled 1 = Enabled This bit will enable the generation of a Reset pulse after a frequency change occurs Disabled 1 = Enabled CY28325-3 Power-on Default Power-on ...
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... Watchdog timer time-out occurs. Under recovery frequency mode, CY28325-2 will not re- spond to any attempt to change the output frequency via the SMBus control bytes. System software can unlock the CY28325-3 from its recovery fre- quency mode by clearing the WD_EN bit. Reserved ...
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... CPU and other output clocks. When it is cleared, the same frequency ratio stated in the Latched FS[4:0] reg- ister will be used. When it is set, the frequency ratio stated in the SEL[4:0] register will be used. Pin Description Latched FS[4:0] inputs. These bits are Read-only. CY28325-3 Power-on Default ...
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... Watchdog timer before they attempt to make a frequency change. If the system hangs and a Watchdog timer time-out occurs, a system reset will be generated and a recovery frequency will be activated. All the related registers are summarized in the following table. Description CY28325-3 Power-on Default ...
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... The ratio of (N+3) and (M+3) need to be greater than “1” [(N+3)/(M+3) > 1]. The following table lists set of N and M values for different frequency output ranges.This example use a fixed value for the M-Value Register and select the CPU output frequency by changing the value of the N-Value Register. CY28325-3 Page [+] Feedback ...
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... Condition Maximum functional voltage Maximum functional voltage Relative Non-functional Functional Functional MIL-STD-883, Method 3015 Mil-Spec 883E Method 1012.1 JEDEC (JESD 51) At 1/8 in. Description CY28325-3 Range of N-Value Register for Different CPU Frequency 97 - 255 127 - 245 Min. Max. Unit –0.5 5.5 V –0.5 5.5 V –0 ...
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... Measured at 1.5V Measured at V CROSS Measured at V CROSS Measured at V CROSS [6] Between 0.8V and 2.0V [6] Between 0.8V and 2.0V Between 2.0V and 0.8V [7] Between 2.0V and 0.8V Measured at 1.5V Measured at 1.5V Measured at 1. Measured at 1. Measured at 1. CY28325-3 Min. Max. Unit /2 2.4 – – 0 –1 mA 2.4 – –1 mA 2.4 – – ...
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... Measured with test loads Measured with test loads Measured with test loads (Single-ended Output (CPU Differential Output 2.5V, duty cycle is measure at 1.25V. DD CY28325-3 Min. Max. Unit t – t – 1000 0.175 1.6 0.175 1.6 – 150 t – t – ...
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... Shrunk Small Outline Package (SSOP) - Tape and Reel- Lead Free Commercial, 0°C to 70°C Document #: 38-07590 Rev. *.* Package Type CY28325-3 Operating Range Commercial, 0°C to 70°C Commercial, 0°C to 70°C Commercial, 0°C to 70°C Page [+] Feedback ...
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... The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. CY28325-3 51-85061-*C ...
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... Document History Page Document Title: CY28325-3 FTG for Via Pentium 4 Chipsets Document Number: 38-07590 Rev. *.* REV. ECN NO. Issue Date ** 224401 See ECN Document #: 38-07590 Rev. *.* Orig. of Change Description of Change RGL New Datasheet CY28325-3 Page [+] Feedback ...