cy25823 Cypress Semiconductor Corporation., cy25823 Datasheet - Page 5

• Manufacturer Part Number: cy25823
• Description: Ck-sscd Spread Spectrum Differential Clock Specification
• Manufacturer: Cypress Semiconductor Corporation.

Document #: 38-07579 Rev. *C
Byte1[7:2] Control Register
Byte 1: [1:0] Control Register (Charge Pump Settings)
Bytes 2 through 5: Reserved Registers
Byte 6: Vendor/Revision ID Register
Spread Enable and Spread Select[3:0]
Spread Enable and Spread Select[3:0] register bits are used
to enable and disable spread spectrum on CLKOUT and to
change the spread modulation. When the spread selection
changes, the CLKOUT output transits to the target spread
selection without deviating from clock specifications.
At device power-up spread spectrum is enabled and hardware
control mode is enabled. The initial spread-spectrum configu-
ration is determined by the S[3:1] pins, which correspond to
the S[3:1] bits in Table 4. The S0 configuration bit is
hard-coded to zero when hardware control mode is selected.
All four spread spectrum configuration bits, S[3:0], can also be
set when the device is in the software control mode.
Charge Pump Select Byte1 [1:0]
Programming these bits (Byte1[1:0]) via I
to have more spread percentage options as described in
Table 5. At the start up the default value for byte1[1:0] bits is
set to ‘00’, this value can be changed via I
spread percentage on CLKOUT and CLKOUT#. Setting the
byte[1:0] bits to ‘11’ allows the user to have a slightly higher
Bit
Bit
Bit
1
0
7
6
5
4
3
2
7
6
5
4
3
2
1
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
1
@Pup
@Pup
@Pup
Default Value
11,12
Pin#
Pin#
–
–
–
–
–
–
–
–
0
0
CLKEN
2
C enables the user
2
C to have higher
One Step Higher Than Default
Name
Name
–
–
–
–
–
–
–
–
1
1
spread percentage than the default value(00). The ‘01’ option
is the highest spread option for maximum EMI reduction.
PWRDWN (Power-down) Clarification
The PWRDWN (Power-down) pin is used to shut off the clock
prior to shutting off power to the device. PWRDWN is an
asynchronous active HIGH input. This signal is synchronized
internally to the device powering down the clock synthesizer.
PWRDWN also is an asynchronous function for powering up
the system. When PWRDWN is high, all clocks are tri-stated
and the oscillator and PLL are also powered down. All clocks
are shut down in a synchronous manner so has not to cause
glitches while transitioning to the stopped state. The CLKIN
input must be on and within specified operating parameters
before PWRDWN is asserted and it must remain in this state
while PWRDWN is asserted, see Figure 1.
When PWRDWN is de-asserted (CLKIN starts after
powerdown de-assertion to meet the IDD≤250µA specifi-
cation) the clocks should remain stopped until the VCO is
stable and within specification (t
Revision ID Bit 3
Revision ID Bit 2
Revision ID Bit 1
Revision ID Bit 0
Vendor ID Bit 3
Vendor ID Bit 2
Vendor ID Bit 1
Vendor ID Bit 0
Reserved set equal to ‘0’
Reserved set equal to ‘0’
Reserved set equal to ‘0’
Reserved set equal to ‘0’
Reserved set equal to ‘0’
CLKOUT/CLKOUT# enable
0 =Disable, 1 = Enable
Two Steps Higher Than Default
Pin Description
Pin Description
STABLE
)., see Figure 2.
1
0
CY25823
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