cy25823 Cypress Semiconductor Corporation., cy25823 Datasheet
cy25823
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cy25823 Summary of contents
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... VDDA VSSA IREF 13 4 VSSIREF CLKOUT 11 6 CLKOUT# 10 VSS 7 SCLK 9 VDD 8 SDATA 16 pin TSSOP • 3901 North First Street • San Jose CY25823 Specification REFOUT CLKOUT Post (SSCG Output) Dividers CLKOUT 95134 • 408-943-2600 Revised September 02, 2004 [+] Feedback ...
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... Table 3 outlines the corresponding byte write and byte read protocol.The combined 7 bits slave address and read/write bit form a complete block write (D4h) or block read (D5h) command. Description Bit 1 2 CY25823 Description Block Read Protocol Description Start Slave address – 7 bits (D5) Read = 0 Acknowledge from slave Page [+] Feedback ...
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... Acknowledge from slave 30:37 Data byte from slave – 8 bits 38 Not Acknowledge 39 Stop Name SS0 – SS1 – SS2 – SS3 – SEL100/96# Select output frequency 100 MHz MHz CY25823 Block Read Protocol Description Byte Read Protocol Description Pin Description Page [+] Feedback ...
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... Down 0.90 Down 1.20 Down 1.40 Down 1.60 Down 1.75 Down 2.20 Down 2.60 Center ±0.38 Center ±0.40 Center ±0.50 Center ±0.60 Center ±0.75 Center ±1.00 Center ±1.15 Center ±1.30 CY25823 Pin Description Spread Amount % 0.65 0.80 0.90 1.10 1.30 1.40 1.80 2.25 ±0.25 ±0.30 ±0.40 ±0.45 ±0.60 ±0.80 ±1.00 ±1.10 Spread Amount % (Charge pump = 01) 0.90 1.10 1.40 1.60 2.00 2.20 2.75 3.30 ±0.40 ± ...
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... When PWRDWN is de-asserted (CLKIN starts after powerdown de-assertion to meet the IDD≤250µA specifi- cation) the clocks should remain stopped until the VCO have higher stable and within specification (t CY25823 Pin Description Two Steps Higher Than Default 1 0 Pin Description ) ...
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... ∼ V REF Document #: 38-07579 Rev Figure 1. Power-down Assertion Off Starting Tstable TpZH Figure 2. Power-down Deassertion 3. 1.1V Figure 3. Current Reference Circuit CY25823 O ff Stable C LK OUT C LK OUT # Page [+] Feedback ...
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... REF voltage. The I is scaled the output stage and I REF as OUT REF The recommended value for R is 475 Ohms, which corre- REF sponds to the I of 2.32mA. REF CY25823 is given OUT Page [+] Feedback ...
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... Measured at 1.5V crossing point Measured between 0.8V and 2.0V (REFOUT with max Lumped capacitive load average over 1-µs duration Over 150 ms Measured at crossing point V OX Measured at crossing point V OX Measured at crossing point V OX Measured at crossing point V OX CY25823 Max. Unit 4 0.5 VDC DD 150 °C 70 ° ...
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... Measure DDA 0.1µ CLKOUT R4 11 CLKOUT# IREF R3 14 475Ω SSIREF SSA Figure 4. Application Schematic CY25823 Min. Max. Unit 175 700 ps – – 3.0 ms – 125 ps – 125 ps 660 850 mv –150 – mv 250 550 mv – ...
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... Ω Figure 6. 0.7V Load Configuration Package Type 16-pin TSSOP (Lead-free) 16-pin TSSOP – Tape and Reel (Lead-free) CY25823 Product Flow Commercial, 0°C to 70°C Commercial, 0°C to 70°C Page [+] Feedback ...
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... DIMENSIONS IN MM[INCHES] MIN. REFERENCE JEDEC MO-153 6.25[0.246] PACKAGE WEIGHT 0.05 gms 6.50[0.256] Z16.173 ZZ16.173 LEAD FREE PKG. 0.25[0.010] 1.10[0.043] MAX. BSC GAUGE 0°-8° PLANE 0.076[0.003] SEATING PLANE CY25823 MAX. PART # STANDARD PKG. 0.50[0.020] 0.09[[0.003] 0.70[0.027] 0.20[0.008] 51-85091-*A Page [+] Feedback ...
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... Document History Page Document Title: CY25823 CK-SSCD Spread Spectrum Differential Clock Specification Document #: 38-07579 Rev. *C Rev. ECN No. Issue Date ** 131662 12/10/03 *A 203801 See ECN *B 252269 See ECN *C 260155 See ECN Document #: 38-07579 Rev. *C Orig. of Change Description of Change RGL New Data Sheet RGL ...