cy25823 Cypress Semiconductor Corporation., cy25823 Datasheet - Page 2

• Manufacturer Part Number: cy25823
• Description: Ck-sscd Spread Spectrum Differential Clock Specification
• Manufacturer: Cypress Semiconductor Corporation.

Document #: 38-07579 Rev. *C
Pin Definitions
Serial Data Interface
To enhance the flexibility and function of the clock synthesizer,
a two-signal serial interface is provided. Through the Serial
Data Interface, various device functions such as individual
clock output buffers can be individually enabled or disabled.
The registers associated with the Serial Data Interface
initializes to their default setting upon power-up, and therefore
use of this interface is optional. Clock device register changes
are normally made upon system initialization, if any are
required. The interface can also be used during system
operation for power management functions.
Table 1. Command Code Definition
Table 2. Block Read and Block Write Protocol
1
2,3,4
5
6
7
8
9
10
11
12
13
14
15
16
Pin No.
Bit
2:8
10
1
9
(6:0)
Bit
7
CLKIN
S[3:1]
PWRDWN
REFOUT/SEL
SCLK
SDATA
VDD
VSS
CLKOUT#
CLKOUT
VSSIREF
IREF
VSSA
VDDA
Start
Slave address – 7 bits (D4)
Write = 0
Acknowledge from slave
0 = Block read or block write operation
1 = Byte read or byte write operation
Byte offset for byte read or byte write operation. For block read or block write operations, these bits should
be '0000000'
Name
Block Write Protocol
Description
Ground
Ground
Ground
Output
Output
Input
Input
Input
Input
Input
3.3V
3.3V
Type
I/O
I/O
3.3V 14.131818-MHz single-ended clock input
Spread Spectrum configuration
3.3V LVTTL input for power-down active high, no pull-up or pull-down
Latched input during power-up, 1 (10K external pull-up) = 100 MHz or 0
(10K external pull-down) = 96 MHz. After power-up it becomes 14.31818-MHz
REFOUT clock.
SMBus-compatible SCLK
SMBus-compatible SDATA
3.3V power supply for logic and outputs
Ground for logic and outputs
0.7V 96-MHz or 100-MHz Spread Spectrum differential clock output
0.7V 96-MHz or 100-MHz Spread Spectrum differential clock output
Current reference ground
Typically a precision 475Ω external resistor is connected between this
pin and VSSIREF to set IOUT (drive current) of CLKOUT differential
driver.
Ground for PLL
3.3V power supply for PLL
Data Protocol
The clock driver serial protocol accepts byte write, byte read,
block write, and block read operation from the controller. For
block write/read operation, the bytes must be accessed in
sequential order from lowest to highest byte (most significant
bit first) with the ability to stop after any complete byte has
been transferred. For byte write and byte read operations, the
system controller can access individual indexed bytes. The
offset of the indexed byte is encoded in the command code,
as described in Table 1.
The block write and block read protocol is outlined in Table 2
while Table 3 outlines the corresponding byte write and byte
read protocol.The combined 7 bits slave address and
read/write bit form a complete block write (D4h) or block read
(D5h) command.
Description
2:8
Bit
10
1
9
Start
Slave address – 7 bits (D5)
Read = 0
Acknowledge from slave
Description
Block Read Protocol
Description
CY25823
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