cy2dp3120 Cypress Semiconductor Corporation., cy2dp3120 Datasheet - Page 2
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cy2dp3120
Manufacturer Part Number
cy2dp3120
Description
1 20 Differential Clock/data Fanout Buffer
Manufacturer
Cypress Semiconductor Corporation.
Datasheet
1.CY2DP3120.pdf
(9 pages)
Document #: 38-07514 Rev.*C
Pin Definitions
Table 1.
Governing Agencies
The following agencies provide specifications that apply to the
CY2DP3120. The agency name and relevant specification is
listed below in Table 2.
Table 2.
3
4
6
5
7
8
9
1,2,14,27,40
52,50,48,46,44,42,39,37,
35,33,31,29,26,24,22,20,
18,16,13,11
51,49,47,45,43,41,38,36,
34,32,30,28,25,23,21,19,
17,15,12,10
JEDEC
Mil-Spec
Notes:
1. In the I/O column, the following notation is used: I for Input, O for Output, PD for Pull-Down, PU for Pull-Up, and PWR for Power
2. In ECL mode (negative power supply mode), V
3. V
V
and are between V
CLK_SEL
EE
BB
Control
Agency Name
is available for use for single-ended bias mode for |3.3V| supplies (not |2.5V|).
is connected to GND (0V) and V
0
1
Pin
CC
CLKA, CLKA# input pair is active (Default condition with no connection to pin)
CLKA can be driven with ECL- or PECL-compatible signals with respective power configurations
CLKB, CLKB# input pair is active.
CLKB can be driven with HSTL-compatible signals with respective power configurations
[1, 2, 3]
and V
EE
JESD 020B (MSL)
JESD 51 (Theta JA)
JESD 8–2 (ECL)
JESD 65–B (skew,jitter)
883E Method 1012.1 (Thermal Theta JC)
CLK_SEL I,PD
CLKA,
VBB
CLKA#
CLKB,
CLKB#
VEE
VCC
Q(0:19)
Q#(0:19) O
.
Name
[3]
[2]
CC
is either +3.3V or +2.5V. In both modes, the input and output levels are referenced to the most positive supply (V
I,PD
O
I,PD/PU ECL/PECL
I,PD
I,PD/PU HSTL
-PWR
+PWR
O
EE
I/O
Specification
is either –3.3V or –2.5V and V
ECL/PECL/HSTL Input clock select
Bias
Power
Power
ECL/PECL
ECL/PECL
ECL/PECL
HSTL
Type
CC
Reference voltage output
Alternate differential input clocks
Alternate differential input clocks
Negative supply
Positive Supply
True output
Complement output
Operation
Differential input clocks
Differential input clocks
is connected to GND (0V). In PECL mode (positive power supply mode),
Description
FastEdge™ Series
CY2DP3120
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