cy2pp3220 Cypress Semiconductor Corporation., cy2pp3220 Datasheet - Page 2

• Manufacturer Part Number: cy2pp3220
• Description: Dual 1 10 Differential Clock / Data Fanout Buffer
• Manufacturer: Cypress Semiconductor Corporation.

Document #: 38-07513 Rev.*C
Pin Definitions
Governing Agencies
The following agencies provide specifications that apply to the
CY2PP3220. The agency name and relevant specification is
listed below in Table 2.
Table 1.
4
5
6
7
8
3,9
1,2,14,27,40
52,50,48,46,44,42,39,37,
35,33
51,49,47,45,43,41,38,36,
34,32
31,29,26,24,22,20,18,16,
13,11
30,28,25,23,21,19,17,15,
12,10
JEDEC
Mil-Spec
Notes:
1. In the I/O column, the following notation is used: I for Input, O for Output, PD for Pull-Down, PU for Pull-Up, and PWR for Power
2. In ECL mode (negative power supply mode), V
3. V
V
and are between V
EE
BB
is available for use for single-ended bias mode for |3.3V| supplies (not |2.5V|).
is connected to GND (0V) and V
Pin
Agency Name
CC
[1, 2, 3]
and V
EE
CLKA,
CLKA#
VBB
CLKB,
CLKB#
VEE
VCC
QA(0:9)
QA#(0:9)
QB(0:9)
QB#(0:9)
.
Name
[3]
[2]
CC
is either +3.3V or +2.5V. In both modes, the input and output levels are referenced to the most positive supply (V
I,PD/PU ECL/PECL ECL/PECL Differential input clocks
I,PD/PU ECL/PECL ECL/PECL Differential input clocks
–PWR
+PWR
EE
I,PD
I,PD
I/O
O
O
O
O
O
is either –3.3V or –2.5V and V
JESD 020B (MSL)
JESD 51 (Theta JA)
JESD 8–2 (ECL)
JESD 65–B (skew,jitter)
883E Method 1012.1 (Thermal Theta JC)
ECL/PECL ECL/PECL Differential input clocks
ECL/PECL ECL/PECL Differential input clocks
ECL/PECL True output
ECL/PECL Complement output
ECL/PECL True output
ECL/PECL Complement output
Power
Power
Type
Bias
Reference Voltage Output
Negative Supply
Positive Supply
CC
is connected to GND (0V). In PECL mode (positive power supply mode),
Specification
Description
FastEdge™ Series
CY2PP3220
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CC
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