MBM29SL800BD Fujitsu Media Devices, MBM29SL800BD Datasheet - Page 32

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MBM29SL800BD

Manufacturer Part Number
MBM29SL800BD
Description
(MBM29SL800TD/BD) FLASH MEMORY CMOS 8 M (1 M X 8/512 K X 16) BIT
Manufacturer
Fujitsu Media Devices
Datasheet
32
MBM29SL800TD
(4) Alternate CE Controlled Program Operation Timing Diagram
Notes : PA is address of the memory location to be programmed.
PD is data to be programmed at byte address.
DQ
D
Figure indicates last two bus cycles out of four bus cycle sequence.
These waveforms are for the 16 mode. (The addresses differ from 8 mode.)
OUT
7
is the output of the complement of the data written to the device.
Address
Data
WE
OE
CE
is the output of the data written to the device.
t
GHEL
t
WS
-10/12
3rd Bus Cycle
555h
t
WC
t
t
A0h
DS
CP
/MBM29SL800BD
t
CPH
t
AS
t
t
WH
DH
PA
t
PD
AH
t
Data Polling
WHWH1
DQ
PA
7
D
OUT
-10/12

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