MBM29SL800BD Fujitsu Media Devices, MBM29SL800BD Datasheet - Page 21

• Manufacturer Part Number: MBM29SL800BD
• Description: (MBM29SL800TD/BD) FLASH MEMORY CMOS 8 M (1 M X 8/512 K X 16) BIT
• Manufacturer: Fujitsu Media Devices

DQ
Toggle Bit II
Reading Toggle Bits DQ
*1 : Successive reads from the erasing or erase-suspend sector will cause DQ
*2 : Reading from the non-erase suspend sector address will indicate logic “1” at the DQ
Program
Erase
Erase-Suspend Read
Erase-Suspend Program
(Erase-Suspended Sector)
See “Hardware Sequence Flags Table”.
This toggle bit II, along with DQ
Algorithm or in Erase Suspend.
Successive reads from the erasing sector will cause DQ
devices are in the erase-suspended-read mode, successive reads from the erase-suspended sector will cause
DQ
address of the non-erase suspended sector will indicate a logic “1” at the DQ
DQ
Program operation is in progress. The behavior of these two status bits, along with that of DQ
as follows :
For example, DQ
(DQ
DIAGRAM.
Furthermore, DQ
mode, DQ
Whenever the system initially begins reading toggle bit status, it must read DQ
to determine whether a toggle bit is toggling. Typically a system would note and store the value of the toggle bit
after the first read. After the second read, the system would compare the new value of the toggle bit with the
first. If the toggle bit is not toggling, the device has completed the program or erase operation. The system can
read array data on DQ
However, if, after the initial two read cycles, the system determines that the toggle bit is still toggling, the system
also should note whether the value of DQ
determine again whether the toggle bit is toggling, since the toggle bit may have stopped toggling just as DQ
went high. If the toggle bit is no longer toggling, the device has successfully completed the program or erase
operation. If it is still toggling, the device did not complete the operation successfully, and the system must write
the reset command to return to reading array data.
The remaining scenario is that the system initially determines that the toggle bit is toggling and DQ
gone high. The system may continue to monitor the toggle bit and DQ
mining the status as described in the previous paragraph. Alternatively, it may choose to perform other system
tasks. In this case, the system must start at the begining of the algorithm when it returns to determine the status
of the operation. (Refer to “Toggle Bit Algorithm” in “ FLOW CHART”.)
2
2
6
2
to toggle. When the devices are in the erase-suspended-program mode, successive reads from the byte
is different from DQ
toggles while DQ
2
toggles if this bit is read from an erasing sector.
Mode
MBM29SL800TD
2
2
and DQ
can also be used to determine which sector is being erased. When the device is in the erase
6
6
7
does not.) See also “Hardware Sequence Flags Table” and “(15) DQ
/DQ
to DQ
2
6
in that DQ
2
can be used together to determine if the erase-suspend-read mode is in progress.
0
on the following read cycle.
6
, can be used to determine whether the devices are in the Embedded Erase
6
toggles only when the standard program or Erase, or Erase Suspend
5
DQ
DQ
DQ
is high (see the section on DQ
Toggle Bit Status
0
1
7
7
7
-10/12
2
to toggle during the Embedded Erase Algorithm. If the
/MBM29SL800BD
Toggle
Toggle
Toggle
DQ
5
1
through successive read cycles, deter-
6
2
5
) . If it is, the system should then
to toggle.
2
bit.
7
to DQ
2
bit.
0
at least twice in a row
2
vs. DQ
Toggle*
7
Toggle
, is summarized
DQ
1*
6
1
” in TIMING
2
2
1
5
-10/12
has not
5
21