MBM29SL800BD Fujitsu Media Devices, MBM29SL800BD Datasheet - Page 31

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MBM29SL800BD

Manufacturer Part Number
MBM29SL800BD
Description
(MBM29SL800TD/BD) FLASH MEMORY CMOS 8 M (1 M X 8/512 K X 16) BIT
Manufacturer
Fujitsu Media Devices
Datasheet
(3) Alternate WE Controlled Program Operation Timing Diagram
Notes : PA is address of the memory location to be programmed.
CE
OE
WE
Address
Data
PD is data to be programmed at byte address.
DQ
D
Figure indicates last two bus cycles out of four bus cycle sequence.
These waveforms are for the 16 mode. (The addresses differ from 8 mode.)
OUT
MBM29SL800TD
7
is the output of the complement of the data written to the device.
is the output of the data written to the device.
t
GHWL
3rd Bus Cycle
t
CS
555h
t
WC
t
t
A0h
WP
DS
t
DH
t
WPH
t
AS
t
CH
PA
t
PD
AH
t
Data Polling
WHWH1
-10/12
DQ
PA
7
/MBM29SL800BD
D
OUT
t
DF
t
t
CE
RC
t
D
OE
OUT
t
OH
-10/12
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