MBM29DS163TE Fujitsu Media Devices, MBM29DS163TE Datasheet - Page 26

• Manufacturer Part Number: MBM29DS163TE
• Description: (MBM29DS163BE/TE) FLASH MEMORY CMOS 16 M (2 M X 8/1 M X 16) BIT
• Manufacturer: Fujitsu Media Devices

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MBM29DS163TE/BE
Byte/Word Programming
Program Suspend/Resume
Chip Erase
The device is programmed on a byte-by-byte (or word-by-word) basis. Programming is a four bus cycle operation.
There are two “unlock” write cycles. These are followed by the program set-up command and data write cycles.
Addresses are latched on the falling edge of CE or WE, whichever happens later and the data is latched on the
rising edge of CE or WE, whichever happens first. The rising edge of CE or WE (whichever happens first) begins
programming. Upon executing the Embedded Program Algorithm command sequence, the system is not required
to provide further controls or timings. The device automatically provides adequate internally generated program
pulses and verify programmed cell margin.
The system can determine the status of the program operation by using DQ
or RY/BY. The Data Polling and Toggle Bit must be performed at the memory location being programmed.
The automatic programming operation is completed when the data on DQ
bit at which the device return to the read mode and addresses are no longer latched. (See “Hardware Sequence
Flags” , Hardware Sequence Flags.) Therefore the device requires that a valid address to the device be supplied
by the system at this particular moment. Hence Data Polling must be performed at the memory location being
programmed.
Any commands written to the chip during this period are ignored. If hardware reset occurs during the programming
operation, it is impossible to guarantee the data being written.
Programming is allowed in any sequence and across sector boundaries. Beware that a data “0” cannot be
programmed back to a “1”. Attempting to do so may either hang up the device or result in an apparent success
according to the data polling algorithm but a read from Read/Reset mode will show that the data is still “0”. Only
erase operations can convert “0”s to “1”s.
“Embedded Program
typical command strings and bus operations.
The Program Suspend command allows the system to interrupt a program operation so that data can be read
from any address. Writing the Program Suspend command (B0h) during the Embedded Program operation
immediately suspends the programming. The Program Suspend command may also be issued during a pro-
gramming operation while an erase is suspended. The bank addresses of sector being programed should be
set when writing the Program Suspend command.
When the Program Suspend command is written during a programming process, the device halts the program
operation within 1 s and updates the status bits.
After the program operation has been suspended, the system can read data from any address. The data at
program-suspended address is not valid. Normal read timing and command definitions apply.
After the Program Resume command (30h) is written, the device reverts to programming. The bank addresses
of sector being suspended should be set when writing the Program Resume command. The system can deter-
mine the status of the program operation using the DQ
operation. See “Write Operation Status” for more information.
The system may also write the autoselect command sequence when the device in the Program Suspend mode.
The device allows reading autoselect codes at the addresses within programming sectors, since the codes are
not stored in the memory. When the device exits the autoselect mode, the device reverts to the Program Suspend
mode, and is ready for another valid operation. See “Autoselect Command Sequence” for more information.
The system must write the Program Resume command (address bits are “Bank Address”) to exit the Program
Suspend mode and continue the programming operation. Further writes of the Resume command are ignored.
Another Program Suspend command can be written after the device has resumed programming.
Chip erase is a six bus cycle operation. There are two “unlock” write cycles. These are followed by writing the
“set-up” command. Two more “unlock” write cycles are then followed by the chip erase command.
TM
Algorithm” in “
FLOW CHART” illustrates the Embedded Program
10
7
or DQ
6
status bits, just as in the standard program
7
7
is equivalent to data written to this
(Data Polling) , DQ
TM
Algorithm using
6
(Toggle Bit) ,