MBM29DL34TF Fujitsu Media Devices, MBM29DL34TF Datasheet - Page 36

• Manufacturer Part Number: MBM29DL34TF
• Description: (MBM29DL34BF/TF) FLASH MEMORY CMOS 32 M (4 M X 8/2 M X 16) BIT
• Manufacturer: Fujitsu Media Devices

36
MBM29DL34TF/BF
*1 : Successive reads from the erasing or erase-suspend sector will cause DQ
*2 : Reading from non-erase suspend sector address will indicate logic “1” at the DQ
20. RY/BY
Ready/Busy
21. Data Protection
22. Low V
23. Write Pulse “Glitch” Protection
Program
Erase
Erase-Suspend Read
Erase-Suspend Program
(Erase-Suspended Sector)
again whether the Toggle Bit is toggling, since the Toggle Bit may have stopped toggling just as DQ
If the Toggle Bit is no longer toggling, the device has successfully completed the program or erase operation. If
it is still toggling, the device did not complete the operation successfully, and the system must write the reset
command to return to reading array data.
The remaining scenario is that the system initially determines that the Toggle bit is toggling and DQ
gone high. The system may continue to monitor the Toggle bit and DQ
mining the status as described in the previous paragraph. Alternatively it may choose to perform other system
tasks. In this case, the system must start at the beginning of the algorithm when it returns to determine the
status of the operation. (Refer to “4. Toggle Bit Algorithm” in
The devices provide a RY/BY open-drain output pin to indicate to the host system that the Embedded Algorithms
are either in progress or has been completed. If the output is low, the devices are busy with either a program or
erase operation. If the output is high, the devices are ready to accept any read/write or erase operation. If the
devices are placed in an Erase Suspend mode, the RY/BY output will be high.
During programming, the RY/BY pin is driven low after the rising edge of the fourth WE pulse. During an erase
operation, the RY/BY pin is driven low after the rising edge of the sixth WE pulse. The RY/BY pin will indicate a
busy condition during the RESET pulse. Refer to “10. RY/BY Timing Diagram during Program/Erase Operations”
and “11. RESET, RY/BY Timing Diagram” in
pin is pulled high in standby mode.
Since this is an open-drain output, the pull-up resistor needs to be connected to V
be connected to the host system via more than one RY/BY pin in parallel.
The devices are designed to offer protection against accidental erasure or programming caused by spurious
system level signals that may exist during power transitions. During power up the devices automatically reset
the internal state machine in the Read mode. Also, with its control register architecture, alteration of the memory
contents only occurs after successful completion of specific multi-bus cycle command sequences.
The devices also incorporate several features to prevent inadvertent write cycles resulting form V
and power-down transitions or system noise.
To avoid initiation of a write cycle during V
than V
disabled. Under this condition, the device will reset to the read mode. Subsequent writes will be ignored until
the V
to prevent unintentional writes when V
If Embedded Erase Algorithm is interrupted, the intervened erasing sector (s) is(are) not valid.
Noise pulses of less than 3 ns (typical) on OE, CE, or WE will not initiate a write cycle.
CC
LKO
level is greater than V
CC
(Min) . If V
Write Inhibit
Mode
CC
V
LKO
LKO
, the command register is disabled and all internal program/erase circuits are
. It is the users responsibility to ensure that the control pins are logically correct
70
CC
Toggle Bit Status Table
is above V
CC
DQ
DQ
DQ
power-up and power-down, a write cycle is locked out for V
0
1
7
7
7
TIMING DIAGRAM for a detailed timing diagram. The RY/BY
LKO
(Min) .
FLOW CHART.)
Toggle
Toggle
Toggle
DQ
5
1
through successive read cycles, deter-
6
2
to toggle.
2
CC
bit.
; multiple of devices may
Toggle *
Toggle *
DQ
1 *
1
CC
2
5
2
went high.
power-up
5
1
1
has not
CC
less