MBM29DL34TF Fujitsu Media Devices, MBM29DL34TF Datasheet - Page 25

• Manufacturer Part Number: MBM29DL34TF
• Description: (MBM29DL34BF/TF) FLASH MEMORY CMOS 32 M (4 M X 8/2 M X 16) BIT
• Manufacturer: Fujitsu Media Devices

5. Read Mode
6. Output Disable
7. Write
8. Sector Group Protection
programmed with its corresponding programming algorithm.
To activate this mode, the programming equipment must force V
then be sequenced from the devices outputs by toggling address A
High or Low except A
= V
The manufacturer and device codes may also be read via the command register, for instances when the device
is erased or programmed in a system without access to high voltage on the A
illustrated in “MBM29DL34TF/BF Command Definitions Table” (
Autoselect Command” in
In Word mode, a read cycle from address 00h returns the manufacturer’s code (Fujitsu
address 01h outputs device code (MBM29DL34TF=2250h, MBM29DL34BF=2253h). Notice that the above
applies to Word mode; the addresses and codes differ from those of Byte mode (Refer to “MBM29DL34TF/BF
Sector Group Protection Verify Autoselect Codes Tables” and “MBM29DL34TF/BF Extended Autoselect Code
Tables” in
The device has two control functions required to obtain data at the outputs. CE is the power control and used
for a device selection. OE is the output control and used to gate data to the output pins .
Address access time (t
access time (t
enable access time is the delay from the falling edge of OE to valid data at the output pins. (Assuming the
addresses have been stable for at least t
power-up, input hardware reset or to change CE pin from “H” or “L”
With the OE input at a logic high level (V
pins to be in a high impedance state.
Device erasure and programming are accomplished via the command register. The contents of the register serve
as inputs to the internal state machine. The state machine outputs dictate the device function.
The command register itself does not occupy any addressable memory location. The register is a latch used to
store the commands, along with the address and data information needed to execute the command. The com-
mand register is written by bringing WE to V
falling edge of WE or CE, whichever starts later; while data is latched on the rising edge of WE or CE, whichever
starts first. Standard microprocessor write timings are used.
The devices feature hardware sector group protection. This feature will disable both program and erase opera-
tions in any combination of twenty five sector groups of memory. (See “Sector Group Addresses Tables
(MBM29DL34TF/BF)” in
protection using programming equipment. The device is shipped with all sector groups that are unprotected.
To activate it, the programming equipment must force V
be set to the sector to be protected. “Sector Address Tables (MBM29DL34TF/BF)” in
ARCHITECTURE define the sector address for each of the seventy one (71) individual sectors, and “Sector
Group Addresses Tables (MBM29DL34TF/BF)” in
group address for each of the twenty five (25) individual group sectors. Programming of the protection circuitry
begins on the falling edge of the WE pulse and is terminated with the rising edge of the same. Sector group
addresses must be held constant during the WE pulse. See “15. Sector Group Protection Timing Diagram” in
waveforms and algorithm.
To verify programming of the protection circuitry, the programming equipment must force V
A
TIMING DIAGRAM and “5. Sector Group Protection Algorithm” in
IH
3
and BYTE = V
A
2
A
0
DEVICE BUS OPERATION.) .
CE
) is the delay from stable addresses and stable CE to valid data at the output pins. The output
V
IL
, A
IL
)” in
0
1
, A
ACC
1
V
, A
) is equal to the delay from stable addresses to valid output data. The chip enable
IH
. The sector group addresses (A
COMMAND DIFINITIONS.)
2
DEVICE BUS OPERATION.)
SECTOR-ERASE ARCHITECTURE) . The user’s side can use the sector group
, A
3
, and A
ACC
6
(A
IH
-t
) , output from the devices are disabled. This will cause the output
-1
OE
IL
) . (See “MBM29DL34TF/BF User Bus Operations Tables (BYTE
, while CE is at V
time.) When reading out a data without changing addresses after
ID
SECTOR-ERASE ARCHITECTURE define the sector
on address pin A
20
IL
, A
and OE is at V
ID
19
MBM29DL34TF/BF
0
, A
on address pin A
DEVICE BUS OPERATION). (Refer to “2.
from V
18
FLOW CHART for sector group protection
, A
9
17
IL
and control pin OE, CE V
, A
to V
9
IH
16
pin. The command sequence is
. Addresses are latched on the
, A
IH
. All addresses can be either
15
9
, A
. Two identifier bytes may
14
, A
04h) . A read cycle at
ID
13
SECTOR-ERASE
on address pin A
, and A
12
IL
) should
and A
70
6
9
25