MBM29BS12DH Fujitsu Media Devices, MBM29BS12DH Datasheet - Page 54

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MBM29BS12DH

Manufacturer Part Number
MBM29BS12DH
Description
(MBM29FS12DH / MBM29BS12DH) BURST MODE FLASH MEMORY CMOS 128M (8M X 16) BIT
Manufacturer
Fujitsu Media Devices
Datasheet
54
MBM29BS/FS12DH
DQ
15
A
22
to DQ
to A
RDY
AVD
CLK
Note : Figure assumes 7 wait states for initial access, synchronous read. D0 to D7 in data waveform
OE
CE
0
0
t
t
AVSC
ACS
High-Z
indicate the order of data within a given 8-word address range, from lowest to highest.
See "Requirements for Synchronous (Burst) Read Operation". The Set Configuration Register
command sequence has been written with A
t
CR
Aa
t
ACH
1
t
CES
t
AVHC
2
t
OES
7 cycles for initial access shown.
t
3
CKA
t
t
IACC
ACC
4
Figure 5
15
5
6
8-word Linear Burst
t
RACC
7
18
D0
= 1; device will output RDY with valid data.
t
BDH
D1
t
BACC
D2
D3
D4
D5
D6
D7
t
CEZ

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