MBM29BS12DH Fujitsu Media Devices, MBM29BS12DH Datasheet - Page 34

• Manufacturer Part Number: MBM29BS12DH
• Description: (MBM29FS12DH / MBM29BS12DH) BURST MODE FLASH MEMORY CMOS 128M (8M X 16) BIT
• Manufacturer: Fujitsu Media Devices

34
MBM29BS/FS12DH
RDY Configuration Setting
Autoselect Command
Address BIt
The device can be set so that RDY goes active either with valid data or one data cycle before active data. Address
bit A
“Configuration Register Table” shows the address bits that determine the configuration register settings for
various device functions.
Flash memories are intended for use in applications where the local CPU alters memory contents. Therefore,
manufacture and device codes must be accessible while the device resides in the target system. PROM pro-
grammers typically access the signature codes by raising A
voltage onto the address lines is not generally desired system design practice.
The device contains an Autoselect command operation to supplement traditional PROM programming method-
ology. The operation is initiated by writing the Autoselect command sequence into the command register.
The Autoselect command sequence is initiated first by writing two unlock cycles. This is followed by a third write
cycle that contains the bank address (BA) and the Autoselect command. Then the manufacture and device
codes can be read from the bank, and actual data from the memory cell can be read from another bank. The
higher order address (A
bank address (BA) set at the third write cycle.
Following the command write ,a read cycle from address (BA)00h returns the manufacturer’s code (Fujitsu=
04h) . And a read cycle at address (BA)01h outputs device code. When 227Eh was output, this indicates that
two additional codes, called Extended Device Codes will be required. Therefore the system may continue reading
out these Extended Device Codes at the address of (BA) 0Eh, as well as at (BA) 0Fh. (Refer to “MBM29BS/
FS12DH Sector Protection Verify Autoselect Codes Table” and “Extended Autoselect Code Table” in “ DEVICE
BUS OPERATIION”. )
The sector state (PPB protection or PPB unprotection) will be informed by address (BA) XX02h. Scanning the
sector group addresses (A
= (0, 0, 0, 0, 0, 0, 1, 0) will produce a logical “1” at device output DQ
A
A
A
A
A
A
A
A
19
18
17
16
15
14
13
12
18
determines this setting; "1" for RDY active with data, "0" for RDY active one clock cycle before valid data.
Programmable
Read Mode
Burst Read
Set Device
Wait State
Function
Clock
Mode
RDY
22
, A
22
, A
0 = Synchronous Read (Burst Mode) Enabled
1 = Asynchronous Mode (Default)
0 = RDY active one clock cycle before data
1 = RDY active with data
0 = Burst starts and data is output on the falling edge of CLK
1 = Burst starts and data is output on the rising edge of CLK
00 = Reserved
01 = 8-word linear with wrap around
10 = 16-word linear with wrap around
11 = 32-word linear with wrap around
000 = Data is valid on the 2th active CLK edge after AVD transition to V
001 = Data is valid on the 3th active CLK edge after AVD transition to V
010 = Data is valid on the 4th active CLK edge after AVD transition to V
011 = Data is valid on the 5th active CLK edge after AVD transition to V
100 = Data is valid on the 6th active CLK edge after AVD transition to V
101 = Data is valid on the 7th active CLK edge after AVD transition to V
110 = Reserved
111 = Reserved
21
, A
21
, A
20
) required for reading out the manufacture and device codes demands the
20
, A
Configuration Register Table
15
19
, A
18
, A
17
, A
16
, A
15
, A
Settings (Binary)
9
14
to a higher voltage. However, multiplexing high
, A
0
for a protected sector group. The programming
13
, and A
12
) while(A
7
, A
6
, A
5
, A
4
, A
3
, A
IH
IH
IH
IH
IH
IH
2
, A
1
,A
0
)