MBM29BS12DH Fujitsu Media Devices, MBM29BS12DH Datasheet - Page 41

• Manufacturer Part Number: MBM29BS12DH
• Description: (MBM29FS12DH / MBM29BS12DH) BURST MODE FLASH MEMORY CMOS 128M (8M X 16) BIT
• Manufacturer: Fujitsu Media Devices

*1: Successive reads from the erasing or erase-suspend sector will cause DQ
*2: Reading from non-erase suspend sector address will indicate logic “1” at the DQ
*3: When the device is se to Asynchronous mode, these status flags should be read by CE toggle.
DQ
Data Polling
In Progress
Time Limits
Exceeded
The device features Data Polling as a method to indicate to the host that the Embedded Algorithms are in
progress or completed. During the Embedded Program Algorithm, an attempt to read the device will produce a
complement of data last written to DQ
read the device will produce true data last written to DQ
read the device will produce a “0” at the DQ
attempt to read device will produce a “1” on DQ
Algorithm” in “ FLOW CHART”.
For programming, the Data Polling is valid after the rising edge of the fourth write pulse in the four write pulse
sequences.
For chip erase and sector erase, the Data Polling is valid after the rising edge of the sixth write pulse in the six
write pulse sequences. Data Polling must be performed at sector addresses of sectors being erased, not pro-
tected sectors. Otherwise the status may become invalid.
If a program address falls within a protected sector, Data Polling on DQ
that bank returns to the read mode. After an erase command sequence is written, if all sectors selected for
erasing are protected, Data Polling on DQ
Once the Embedded Algorithm operation is close to being completed, the device data pins (DQ
asynchronously while the output enable (OE) is asserted low. This means that device is driving status information
on DQ
the DQ
operation and DQ
DQ
The Data Polling feature is active only during the Embedded Programming Algorithm, Embedded Erase Algorithm
or sector erase time-out. (See “Hardware Sequence Flags Table”. )
See “Data Polling Timings/Toggle Bit Timings (During Embedded Algorithm) ” and “Synchronous Data Polling
Timings/Toggle Bit Timings” in “ TIMING DIAGRAM” for the Data Polling timing specifications and diagrams.
7
7
will be read on successive read attempts.
7
7
at one instant, and then that byte’s valid data at the next instant. Depending on when the system samples
output, it may read the status or valid data. Even if device has completed the Embedded Algorithm
Embedded Program Algorithm
Embedded
Erase
Algorithm
Erase
Suspended
Mode
Embedded Program Algorithm
Embedded Erase Algorithm
Erase
Suspended
Mode
7
has a valid data, data outputs on DQ
Status
Erase Sector
Non-Erase Sector
Erase Suspend Read
(Erase Suspended Sector)
Erase Suspend Read
(Non-Erase Suspended Sector)
Erase Suspend Program
(Non-Erase Suspended Sector)
Erase Suspend Program
(Non-Erase Suspended Sector)
Hardware Sequence Flags Table
7
. Upon completion of the Embedded Program Algorithm, an attempt to
7
is active for approximately 400 s, then the bank returns to read mode.
7
output. Upon completion of the Embedded Erase Algorithm, an
7
. The flowchart for Data Polling (DQ
7
. During the Embedded Erase Algorithm, an attempt to
0
to DQ
Data
DQ
DQ
DQ
DQ
DQ
0
1
0
7
7
7
7
7
6
MBM29BS/FS12DH
may still be invalid. The valid data on DQ
No Toggle
Toggle
Toggle
Toggle
Toggle
Toggle
Toggle
Data
DQ
*
7
3
is active for approximately 1 s, then
6
2
to toggle.
Data
DQ
2
0
0
0
0
1
1
1
bit.
7
5
) is shown in “Data Polling
Data
DQ
0
1
0
0
0
1
0
3
7
No Toggle*
) may change
No Toggle*
No Toggle*
No Toggle*
Toggle*
Toggle
Data
DQ
N/A
N/A
2
0
1
15
2,
to
3
3
*
3
3
41