FS6377-01g ON Semiconductor, FS6377-01g Datasheet - Page 6

• Manufacturer Part Number: FS6377-01g
• Description: Programmable 3-PLL Clock Generator IC
• Manufacturer: ON Semiconductor

AMI Semiconductor
www.amis.com
FS6377-01/FS6377-01g Programmable 3-PLL Clock Generator IC
A6
1
5.1.2 START Data Transfer
A high to low transition of the SDA line while the SCL input
is high indicates a START condition. All commands to the
device must be preceded by a START condition.
5.1.3 STOP Data Transfer
A low to high transition of the SDA line while SCL is held
high indicates a STOP condition. All commands to the
device must be followed by a STOP condition.
5.1.4 Data Valid
The state of the SDA line represents valid data if the SDA
line is stable for the duration of the high period of the SCL
line after a START condition occurs. The data on the SDA
line must be changed only during the low period of the
SCL signal. There is one clock pulse per data bit.
Each data transfer is initiated by a START condition and
5.1.5 Acknowledge
When addressed, the receiving device is required to
generate an acknowledge after each byte is received. The
master device must generate an extra clock pulse to
coincide with the acknowledge bit. The acknowledging
device must pull the SDA line low during the high period of
the master acknowledge clock pulse. Setup and hold
times must be taken into account.
5.2 I
All programmable registers can be accessed randomly or
sequentially via this bi-directional two wire digital interface.
The device accepts the following I
5.2.1 Slave Address
After generating a START condition, the bus master
broadcasts a seven-bit slave address followed by a R/W
bit. The address of the device is:
5.2.2 Random Register Write Procedure
Random write operations allow the master to directly write
to any register. To initiate a write procedure, the R/W bit
that is transmitted after the seven-bit device address is a
logic-low. This indicates to the addressed slave device that
2
C-bus Operation
A5
0
A4
1
A3
1
A2
X
2
C-bus commands.
A1
0
A0
0
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terminated with a STOP condition. The number of data
bytes transferred between START and STOP conditions is
determined by the master device, and can continue
indefinitely. However, data that is overwritten to the device
after the first sixteen bytes will overflow into the first
register, then the second, and so on, in a first-in, first-
overwritten fashion.
The master must signal an end of data to the slave by not
generating an acknowledge bit on the last byte that has
been read (clocked) out of the slave. In this case, the
slave must leave the SDA line high to enable the master
to generate a STOP condition.
where X is controlled by the logic level at the ADDR pin.
The variable ADDR bit allows two different devices to exist
on the same bus. Note that every device on an I
must have a unique address to avoid bus conflicts. The
default address sets A2 to one via the pull-up on the ADDR
pin.
a register address will follow after the slave device
acknowledges its device address. The register address is
written into the slave's address pointer. Following an
acknowledge by the slave, the master is allowed to write
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2
C-bus
Data Sheet