FS6377-01g ON Semiconductor, FS6377-01g Datasheet

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... FS6377-01/FS6377-01g Programmable 3-PLL Clock Generator IC 1.0 Features • Three on-chip PLLs with programmable reference and feedback dividers • Four independently programmable muxes and post dividers • I C™-bus serial interface 2 • Programmable power-down of all PLLs and output clock drivers 2.0 Description ...

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... FS6377-01/FS6377-01g Programmable 3-PLL Clock Generator IC Table 1. Pin Descriptions Pin Type Name SDA SEL_CD VSS 5 AI XIN 6 AO XOUT VDD 9 DI ADDR CLK_D 11 P VSS 12 DO CLK_C 13 DO CLK_B 14 P VDD 15 DO ...

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... FS6377-01/FS6377-01g Programmable 3-PLL Clock Generator IC 3.1.1 Reference Divider The reference divider is designed for low phase jitter. The divider accepts the output of the reference oscillator and provides a divided-down frequency to the PFD. The reference divider is an 8-bit divider, and can be 3.1.2 Feedback Divider The feedback divider is based on a dual-modulus pre- scaler technique ...

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... FS6377-01/FS6377-01g Programmable 3-PLL Clock Generator IC 3.1.3 Feedback Divider Programming For proper operation of the feedback divider, the A-counter must be programmed only for values that are less than or equal to the M-counter. Therefore, not all divider moduli below 56 are available for use. The selection of divider Table 2 ...

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... FS6377-01/FS6377-01g Programmable 3-PLL Clock Generator IC 4.1 SEL_CD Input The SEL_CD pin provides a way to alter the operation of PLL C, muxes C and D and post dividers C and D without having to reprogram the device. A logic-low on the SEL_CD pin selects the control bits with a "C1" or "D1" ...

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... FS6377-01/FS6377-01g Programmable 3-PLL Clock Generator IC 5.1.2 START Data Transfer A high to low transition of the SDA line while the SCL input is high indicates a START condition. All commands to the device must be preceded by a START condition. 5.1.3 STOP Data Transfer A low to high transition of the SDA line while SCL is held high indicates a STOP condition ...

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... FS6377-01/FS6377-01g Programmable 3-PLL Clock Generator IC eight bits of data into the addressed register. A final acknowledge is returned by the device, and the master generates a STOP condition. 5.2.3 Random Register Read Procedure Random read operations allow the master to directly read from any register. To perform a read procedure, the R/W bit that is transmitted after the seven-bit address is a logic- low the register write procedure ...

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... FS6377-01/FS6377-01g Programmable 3-PLL Clock Generator IC S DEVICE ADDRESS W A REGISTER ADDRESS 7-bit Receive Register Address Device Address Acknowledge START WRITE Command Command From bus host to device Figure 5: Random Register Write Procedure S DEVICE ADDRESS W A REGISTER ADDRESS 7-bit Receive Register Address ...

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... FS6377-01/FS6377-01g Programmable 3-PLL Clock Generator IC 6.0 Programming Information Table 3. Register Map ADDRESS BIT 7 MUX_D2[1:0] BYTE 15 (selected via SEL_CD = 1) BYTE 14 (selected via SEL_CD = 1) BYTE 13 (selected via SEL_CD = 0) BYTE 12 MUX_D1[1:0] BYTE 11 (selected via SEL_CD = 0) BYTE 10 BYTE 9 MUX_C1[1:0] BYTE 8 (selected via SEL_CD = 0) BYTE 7 BYTE 6 ...

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... FS6377-01/FS6377-01g Programmable 3-PLL Clock Generator IC Table 4. Power-Down Bits Name Description Power-Down PLL A Bit = 0 PDPLL_A (Bit 21) Bit = 1 Power-Down PLL B Bit = 0 PDPLL_B (Bit 45) Bit = 1 Power-Down PLL C Bit = 0 PDPLL_C (Bit 69) Bit = 1 Reserved (0) Set these reserved bits to zero (0) (Bit 69) Power-Down POST divider A Bit = 0 PDPOSTA ...

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... FS6377-01/FS6377-01g Programmable 3-PLL Clock Generator IC Table 8. PLL Tuning Bits Name Description Loop Filter Time Constant A Bit = 0 LFTC_A (Bit 20) Bit = 1 Loop Filter Time Constant B Bit = 0 LFTC_B (Bit 44) Bit = 1 Loop Filter Time Constant C1 selected when the SEL_CD pin = 0 Bit = 0 LFTC_C1 (Bit 68) ...

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... FS6377-01/FS6377-01g Programmable 3-PLL Clock Generator IC 7.0 Electrical Specifications Table 10. Absolute Maximum Ratings Parameter Supply Voltage ground) SS Input Voltage, dc Output Voltage, dc Input Clamp Current < Output Clamp Current < Storage Temperature Range (non-condensing) Ambient Temperature Range, Under Bias ...

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... FS6377-01/FS6377-01g Programmable 3-PLL Clock Generator IC Table 12. DC Electrical Specifications Parameter Overall Supply Current, Dynamic, With Loaded Outputs Supply Current, Static Power-Down, Output Enable Pins (PD, OE) High-Level Input Voltage Low-Level Input Voltage Hysteresis Voltage High-Level Input Current Low-Level Input Current (pull-up) ...

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... FS6377-01/FS6377-01g Programmable 3-PLL Clock Generator IC Low Drive Current (mA) Voltage Voltage (V) Min. Typ. Max 104 2 108 112 3 117 119 4 ...

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... FS6377-01/FS6377-01g Programmable 3-PLL Clock Generator IC 110 All outputs at the same frequency 100 All outputs at 200MHz except output under test 5.0V; Reference Frequency = 27.00MHz; VCO Frequency = 200MHz All outputs at the same frequency All outputs at 100MHz ...

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... FS6377-01/FS6377-01g Programmable 3-PLL Clock Generator IC Table 13. AC Timing Specifications Parameter Symbol Overall Output Frequency VCO Frequency* f VCO VCO Gain* A Loop Filter Time Constant* Rise Time Fall Time Tristate Enable Delay* t PZL, Tristate Disable Delay* t PZL, Clock Stabilization Time* ...

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... FS6377-01/FS6377-01g Programmable 3-PLL Clock Generator IC Table 13. AC Timing Specifications, Continued Parameter Clock Outputs (PLL B clock via CLK_B pin) Duty Cycle* (t))* Jitter, Long Term (s y Jitter, Period (peak-peak)* Clock Outputs (PLL_C clock via CLK_C pin) Duty Cycle* (t))* Jitter, Long Term (s y Jitter, Period (peak-peak)* ...

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... FS6377-01/FS6377-01g Programmable 3-PLL Clock Generator IC Table 14. Serial Interface Timing Specifications Parameter Clock Frequency Bus Free Time Between STOP and START t Set-up Time, START (repeated) Hold Time, START Set-up Time, Data Input Hold Time, Data Input Output Data Valid From Clock ...

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... FS6377-01/FS6377-01g Programmable 3-PLL Clock Generator IC 8.0 Package Information - For Both ‘Green’ and ‘Non-Green’ Table 15. 16-pin SOIC (0.150”) Package Dimensions Dimensions Inches Millimeters Min. Max. Min. A 0.061 0.068 1.55 A1 0.004 0.0098 0.102 A2 0.055 0.061 1.40 B 0.013 0.019 0.33 C 0.0075 0.0098 0.191 D 0.386 ...

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... FS6377-01/FS6377-01g Programmable 3-PLL Clock Generator IC 10.0 Demonstration Software Windows 3.1x/95/98-based software is available from AMI Semiconductor that illustrates the capabilities of the FS6377. The software can operate under Windows NT. Contact your local sales representative or the company directly for more information. 10.1 Software Requirements · PC running MS Windows 3.1x or 95/98. Software runs on Windows calculation mode only. · ...

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... FS6377-01/FS6377-01g Programmable 3-PLL Clock Generator IC 10.3.1 Example Programming Type a value for the crystal resonator frequency in MHz in the reference crystal box. This frequency provides the basis for all of the PLL calculations that follow. Next, click on the PLL A box. A pop-up screen similar to Figure 14 should appear. Type in a desired output clock frequency in MHz, set the operating voltage (3 ...