FS6377-01g ON Semiconductor, FS6377-01g Datasheet - Page 21

• Manufacturer Part Number: FS6377-01g
• Description: Programmable 3-PLL Clock Generator IC
• Manufacturer: ON Semiconductor

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FS6377-01/FS6377-01g Programmable 3-PLL Clock Generator IC
10.3.1 Example Programming
Type a value for the crystal resonator frequency in MHz in
the reference crystal box. This frequency provides the
basis for all of the PLL calculations that follow.
Next, click on the PLL A box. A pop-up screen similar to
Figure 14 should appear. Type in a desired output clock
frequency in MHz, set the operating voltage (3.3V or 5V)
and the desired maximum output frequency error.
Pressing calculate solutions generates several possible
divider and VCO-speed combinations.
For a 100MHz output, the VCO should ideally operate at a
higher frequency, and the reference and feedback dividers
should be as small as possible. In this example, highlight
Solution #7. Notice the VCO operates at 200MHz with a
post divider of two to obtain an optimal 50 percent duty
cycle.
Now choose which mux and post divider to use (that is,
choose an output pin for the 100MHz output). Selecting A
places the PostDiv value in Solution #7 into post divider A
and switches mux A to take the output of PLL A.
The PLL screen should disappear, and now the value in
the PLL A box is the new VCO frequency chosen in
Solution #7. Also note that mux A has been switched to
PLL A and the post pivider A has the chosen 100MHz
output displayed.
Repeat the steps for PLL B.
PLL C supports two different output frequencies
depending on the setting of the SEL_CD pin. Both mux C
2
C is a licensed trademark of Philips Electronics, N.V. AMI Semiconductor reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.
Figure 14: PLL Screen
21
and mux D are also affected by the logic level on the
SEL_CD pin, as are the post dividers C and D.
Click on PLL C1 to open the PLL screen. Set a desired
frequency, however, now choose the post divider B as the
output divider. Notice the post divider box has split in two
(as shown in Figure 15). The post divider B box now
shows that the divider is dependent on the setting of the
SEL_CD pin for as long as mux B is the PLL C output.
Clicking on post divider A reveals a pull-down menu
provided to permit adjustment of the post divider value
independently of the PLL screen. A typical menu is shown
in Figure 15. The range of possible post divider values is
also given in Table 7.
The register settings are shown to the left in the screen
shown in Figure 13. Clicking on a register location
displays a screen shown in Figure 16. Individual bits can
be poked, or the entire register value can be changed.
Figure 16: Register Screen
Post Divider Menu
Figure 15:
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