FS6377-01g ON Semiconductor, FS6377-01g Datasheet - Page 5

• Manufacturer Part Number: FS6377-01g
• Description: Programmable 3-PLL Clock Generator IC
• Manufacturer: ON Semiconductor

AMI Semiconductor
www.amis.com
FS6377-01/FS6377-01g Programmable 3-PLL Clock Generator IC
4.1 SEL_CD Input
The SEL_CD pin provides a way to alter the operation of
PLL C, muxes C and D and post dividers C and D without
having to reprogram the device. A logic-low on the
SEL_CD pin selects the control bits with a "C1" or "D1"
notation, per Table 3. A logic-high on the SEL_CD pin
selects the control bits with "C2" or "D2" notation, per
4.2 Power-Down and Output Enable
A logic-high on the PD pin powers down only those
portions of the FS6377 which have their respective
powerdown control bits enabled. Note that the PD pin has
an internal pull-up.
When a post divider is powered down, the associated
output driver is forced low. When all PLLs and post
4.3 Oscillator Overdrive
For applications where an external reference clock is
provided (and the crystal oscillator is not required), the
reference clock should be connected to XOUT and XIN
should be left unconnected (float).
For best results, make sure the reference clock signal is
as jitter-free as possible, can drive a 40pF load with fast
generates the START and STOP conditions while the
device works as a slave. Both master and slave can
operate as a transmitter or receiver, but the master device
5.1 Bus Conditions
Data transfer on the bus can only be initiated when the bus
is not busy. During the data transfer, the data line (SDA)
must remain stable whenever the clock line (SCL) is high.
Changes in the data line while the clock line is high will be
5.1.1 Not Busy
Both the data (SDA) and clock (SCL) lines remain high to
indicate the bus is not busy.
5.0 I
2
C-bus Control Interface
This device is a read/write slave device
meeting all Philips I
except a "general call." The bus has to be
controlled by a master device that generates
the serial clock SCL, controls bus access and
2
C-bus specifications
5
Table 3.
Note that changing between two running frequencies us-
ing the SEL_CD pin may produce glitches in the output,
especially if the post-divider(s) is/are altered.
dividers are powered down the crystal oscillator is also
powered down. The XIN pin is forced low, and the XOUT
pin is pulled high.
A logic-low on the OE pin tristates all output clocks. Note
that this pin has an internal pull-up.
rise and fall times and can swing rail-to-rail.
If the reference clock is not a rail-to-rail signal, the refer-
ence must be AC coupled to XOUT through a 0.01mF or
0.1mF capacitor. A minimum 1V peak-to-peak signal is
required to drive the internal differential oscillator buffer.
determines which mode is activated. A device that sends
data onto the bus is defined as the transmitter, and a
device receiving data as the receiver.
I
percentage of the power supply (V
corresponds to a nominal voltage of V
corresponds to ground (V
interpreted by the device as a START or STOP condition.
The following bus conditions are defined by the I
protocol.
2
C-bus logic levels noted herein are based on a
SS
).
DD
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, while a logic-zero
DD
). A logic-one
2
C-bus
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