LTC3553 Linear Technology Corporation, LTC3553 Datasheet - Page 23

• Manufacturer Part Number: LTC3553
• Description: Micropower USB Power Manager
• Manufacturer: Linear Technology Corporation

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OPERATION
The switching regulator input supply should be bypassed
with a 2.2μF capacitor. Consult with capacitor manufac-
turers for detailed information on their selection and
specifi cations of ceramic capacitors. Many manufacturers
now offer very thin (<1mm tall) ceramic capacitors ideal
for use in height-restricted designs. Table 2 shows a list
of several ceramic capacitor manufacturers.
LOW DROPOUT LINEAR REGULATOR (LDO)
The LDO regulator supports a load of up to 150mA. The
LDO takes power from the V
output pin with the goal of bringing the LDO_FB feedback
pin voltage to 0.8V. Usually, a resistor divider is connected
between the LDO’s output pin, feedback pin and ground,
in order to close the control loop and program the output
voltage. For stability, the LDO output must be bypassed
to ground with at least a 1μF ceramic capacitor.
The LDO is enabled or disabled via the pushbutton interface.
In cases where the LDO is disabled and the PowerPath
is actively driving V
switched in to help bring the output to ground. When the
LDO is enabled, a soft-start circuit ramps its regulation
point from zero to fi nal value over a period of roughly
0.2ms, reducing the required V
The LDO has two input voltage requirements. The LDO’s
quiescent bias current is supplied through an internal
connection to the USB PowerPath V
power input is taken from the V
LDO operation, the V
voltage no greater than V
OUT
INLDO
, an internal pull-down resistor is
OUT
INLDO
pin must be connected to a
. For example, V
INLDO
pin and drives the LDO
INLDO
OUT
inrush current.
pin. For proper
pin. The LDO’s
INLDO
can
be connected to V
Connecting V
in loss of regulation.
Output Voltage Programming
Figure 4 shows the LDO regulator application circuit.
Program the LDO output voltage, V
and R2 such that:
Standby Mode LDO Operation (STBY Pin High)
To reduce battery drain current in applications with a
static memory keep-alive or other ultralow quiescent
current state, the LDO may be placed into standby mode
V
LDO
LDO
ENABLE
= 0.8V •
Figure 4. LDO Application Circuit
INLDO
0
1
⎛
⎜
⎝
R2
OUT
to a voltage exceeding V
R1
GND
+1
, or to the buck regulator output.
V
INLDO
⎞
⎟
⎠
MP
LDO_FB
0.8V
LDO
LDO
R1
R2
3553 F04
, by choosing R1
LTC3553
OUT
C
OUT
may result
LDO
OUTPUT
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