LTC2424 Linear Technology, LTC2424 Datasheet - Page 14

• Manufacturer Part Number: LTC2424
• Description: 4-/8-Channel 20-Bit uPower No Latency ADCs
• Manufacturer: Linear Technology

APPLICATIONS
LTC2424/LTC2428
At 100 samples/second, the LTC2424/LTC2428 can be
used to capture transient data. This is useful for monitor-
ing settling or auto gain ranging in a system. The LTC2424/
LTC2428 can monitor signals at an output rate of 100
samples/second. After acquiring 100 samples/second data,
the F
110dB and the highest possible DC accuracy. The no
latency architecture of the LTC2424/LTC2428 allows con-
secutive readings (one at 100 samples/second the next at
7.5 samples/second) without interaction between the two
readings.
As shown in Figure 11, the LTC2424/LTC2428 can cap-
ture transient data with 90dB of dynamic range (with a
14
O
pin may be driven LOW enabling 60Hz rejection to
–0.05
–0.10
–0.15
–0.20
0.20
0.15
0.10
0.05
–10
–2
–4
–6
–8
6
4
2
0
0
Figure 10. Total Unadjusted Error at
7.5 Samples/Second (No Averaging)
0
Figure 11a. Digitized Waveform
500ms
0.5
U
INPUT VOLTAGE (V)
INFORMATION
1
TIME (SEC)
U
1.5
W
V
V
2
CC
REF
f
IN
24248 F11a
24248 F10
= 5V
= 2Hz
= 5V
2.5
Figure 11. Transient Signal Acquisition
5
U
300mV
performance of the LTC2424/LTC2428 enables signals to
be digitized independent of a large DC offset. Figures 12a
and 12b show the dynamic performance with a 15Hz
signal superimposed on a 2V DC level. The same signal
with no DC level is shown in Figures 12c and 12d.
SERIAL INTERFACE
The LTC2424/LTC2428 transmit the conversion results,
program the channel selection, and receive the start of
conversion command through a synchronous 4-wire in-
terface (SCK = CLK, CSADC = CSMUX). During the conver-
sion and sleep states, this interface can be used to assess
the converter status. While in the sleep state this interface
may be used to program an input channel. During the data
output state, it is used to read the conversion result.
ADC Serial Clock Input/Output (SCK)
The serial clock signal present on SCK (Pin 25) is used to
synchronize the data transfer. Each bit of data is shifted out
of the SDO pin on the falling edge of the serial clock.
In the Internal SCK mode of operation, the SCK pin is an
output and the LTC2424/LTC2428 creates its own serial
clock by dividing the internal conversion clock by 8. In the
External SCK mode of operation, the SCK pin is used as
input. The internal or external SCK mode is selected on
power-up and then reselected every time a HIGH-to-LOW
transition is detected at the CSADC pin. If SCK is HIGH or
P-P
–100
–120
–20
–40
–80
–60
input signal at 2Hz). The exceptional DC
0
0
Figure 11b. Output FFT
FREQUENCY (Hz)
25
2Hz
100sps
0V OFFSET
24248 F11b
50