LTC2424 Linear Technology, LTC2424 Datasheet - Page 11

• Manufacturer Part Number: LTC2424
• Description: 4-/8-Channel 20-Bit uPower No Latency ADCs
• Manufacturer: Linear Technology

APPLICATIONS
Table 3. Logic Table for Channel Selection
*Not used for the LTC2424.
CHANNEL STATUS
Table 2. LTC2424/LTC2428 Output Data Format
Input Voltage
V
9/8 • V
V
V
3/4V
3/4V
1/2V
1/2V
1/4V
1/4V
0
–1LSB
–1/8 • V
V
*The sign bit changes state during the 0 code.
IN
REF
REF
+
IN
/0
CSMUX/CSADC
All Off
CH4*
CH5*
CH6*
CH7*
> 9/8 • V
< –1/8 • V
CH0
CH1
CH2
CH3
–
REF
REF
REF
REF
REF
REF
+ 1LSB
REF
REF
SCK/CLK
+ 1LSB
+ 1LSB
+ 1LSB
SDO
REF
D
REF
IN
EN
U
EN
Bit 23
0
1
1
1
1
1
1
1
1
EOC
D2
INFORMATION
0
0
0
0
0
0
0
0
0
0
0
0
0
0
U
Hi-Z
D1
Bit 22
DMY
D2
X
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
D0
Figure 4. Typical Data Input/Output Timing
Bit 21
1/0*
SIG
D1
1
1
1
1
1
1
1
1
1
1
0
0
0
X
0
0
1
1
0
0
1
1
EOC
BIT 23
U
Bit 20
BIT 22
EXR
“0”
1
1
1
0
0
0
0
0
0
0
0
1
1
1
D0
X
0
1
0
1
0
1
0
1
SIG
Bit 19
MSB
0
0
0
1
1
1
1
0
0
0
0
1
1
1
EXT
Frequency Rejection Selection (F
The LTC2424/LTC2428 internal oscillator provides better
than 110dB normal mode rejection at the line frequency
and all its harmonics for 50Hz 2% or 60Hz 2%. For
60Hz rejection, F
(Pin 1) while for 50Hz rejection the F
connected to V
The selection of 50Hz or 60Hz rejection can also be made
by driving F
change during the sleep or data output states will not
disturb the converter operation. If the selection is made
Bit 18
MSB
0
0
0
1
1
0
0
1
1
0
0
1
1
1
DON’T CARE
O
Bit 17
0
0
0
1
0
1
0
1
0
1
0
1
1
1
to an appropriate logic level. A selection
CC
LSB
BIT 0
O
(Pin 2).
(Pin 26) should be connected to GND
Bit 16
1
1
0
1
0
1
0
1
0
1
0
1
0
0
LTC2424/LTC2428
Bit 15
1
1
0
1
0
1
0
1
0
1
0
1
0
0
t
Hi-Z
CONV
O
Pin Connection)
…
...
...
...
...
...
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...
...
...
...
...
...
...
...
O
pin should be
24248 F04
Bit 0
LSB
1
1
0
1
0
1
0
1
0
1
0
1
0
0
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