LTC2410 Linear Technology, LTC2410 Datasheet - Page 8

• Manufacturer Part Number: LTC2410
• Description: 24-Bit No Latency ADC with Differential Input and Differential Reference
• Manufacturer: Linear Technology

APPLICATIO S I FOR ATIO
LTC2410
Once CS is pulled LOW, the device begins outputting the
conversion result. There is no latency in the conversion
result. The data output corresponds to the conversion just
performed. This result is shifted out on the serial data out
pin (SDO) under the control of the serial clock (SCK). Data
is updated on the falling edge of SCK allowing the user to
reliably latch data on the rising edge of SCK (see Figure 3).
The data output state is concluded once 32 bits are read
out of the ADC or when CS is brought HIGH. The device
automatically initiates a new conversion and the cycle
repeats.
Through timing control of the CS and SCK pins, the
LTC2410 offers several flexible modes of operation
(internal or external SCK and free-running conversion
modes). These various modes do not require program-
ming configuration registers; moreover, they do not dis-
turb the cyclic operation described above. These modes of
operation are described in detail in the Serial Interface
Timing Modes section.
Conversion Clock
A major advantage the delta-sigma converter offers over
conventional type converters is an on-chip digital filter
(commonly implemented as a Sinc or Comb filter). For
high resolution, low frequency applications, this filter is
typically designed to reject line frequencies of 50 or 60Hz
plus their harmonics. The filter rejection performance is
directly related to the accuracy of the converter system
clock. The LTC2410 incorporates a highly accurate on-
chip oscillator. This eliminates the need for external fre-
quency setting components such as crystals or oscilla-
tors. Clocked by the on-chip oscillator, the LTC2410
achieves a minimum of 110dB rejection at the line fre-
quency (50Hz or 60Hz 2%).
Ease of Use
The LTC2410 data output has no latency, filter settling
delay or redundant data associated with the conversion
cycle. There is a one-to-one correspondence between the
conversion and the output data. Therefore, multiplexing
multiple analog voltages is easy.
8
U
U
W
U
The LTC2410 performs offset and full-scale calibrations
every conversion cycle. This calibration is transparent to
the user and has no effect on the cyclic operation de-
scribed above. The advantage of continuous calibration is
extreme stability of offset and full-scale readings with re-
spect to time, supply voltage change and temperature drift.
Power-Up Sequence
The LTC2410 automatically enters an internal reset state
when the power supply voltage V
mately 2.2V. This feature guarantees the integrity of the
conversion result and of the serial interface mode selec-
tion. (See the 2-wire I/O sections in the Serial Interface
Timing Modes section.)
When the V
the converter creates an internal power-on-reset (POR)
signal with a duration of approximately 0.5ms. The POR
signal clears all internal registers. Following the POR
signal, the LTC2410 starts a normal conversion cycle and
follows the succession of states described above. The first
conversion result following POR is accurate within the
specifications of the device if the power supply voltage is
restored within the operating range (2.7V to 5.5V) before
the end of the POR time interval.
Reference Voltage Range
This converter accepts a truly differential external refer-
ence voltage. The absolute/common mode voltage speci-
fication for the REF
from GND to V
REF
The LTC2410 can accept a differential reference voltage
from 0.1V to V
mined by the thermal noise of the front-end circuits, and
as such, its value in nanovolts is nearly constant with
reference voltage. A decrease in reference voltage will not
significantly improve the converter’s effective resolution.
On the other hand, a reduced reference voltage will im-
prove the converter’s overall INL performance. A reduced
reference voltage will also improve the converter perfor-
mance when operated with an external conversion clock
(external F
rates (see the Output Data Rate section).
+
pin must always be more positive than the REF
O
CC
signal) at substantially higher output data
voltage rises above this critical threshold,
CC
CC
. The converter output noise is deter-
. For correct converter operation, the
+
and REF
–
pins covers the entire range
CC
drops below approxi-
–
pin.