LTC2410 Linear Technology, LTC2410 Datasheet - Page 18

• Manufacturer Part Number: LTC2410
• Description: 24-Bit No Latency ADC with Differential Input and Differential Reference
• Manufacturer: Linear Technology

APPLICATIO S I FOR ATIO
LTC2410
Internal Serial Clock, Autostart Conversion
This timing mode is identical to the internal serial clock,
2-wire I/O described above with one additional feature.
Instead of grounding CS, an external timing capacitor is
tied to CS.
While the conversion is in progress, the CS pin is held
HIGH by an internal weak pull-up. Once the conversion is
complete, the device enters the low power sleep state and
an internal 25nA current source begins discharging the
capacitor tied to CS, see Figure 11. The time the converter
spends in the sleep state is determined by the value of the
external timing capacitor, see Figures 12 and 13. Once the
voltage at CS falls below an internal threshold ( 1.4V), the
device automatically begins outputting data. The data
output cycle begins on the first rising edge of SCK and
ends on the 32nd rising edge. Data is shifted out the SDO
pin on each falling edge of SCK. The internally generated
serial clock is output to the SCK pin. This signal may be
18
(INTERNAL)
GND
SDO
SCK
V
CS
CC
U
CONVERSION
U
Hi-Z
W
Figure 11. Internal Serial Clock, Autostart Operation
ANALOG INPUT RANGE
SLEEP
–0.5V
REF
1, 7, 8, 9, 10, 15, 16
0.1V TO V
REFERENCE
TO 0.5V
U
VOLTAGE
1 F
2.7V TO 5.5V
REF
CC
BIT 31
EOC
2
3
4
5
6
V
REF
REF
IN
IN
GND
CC
+
–
LTC2410
used to shift the conversion result into external circuitry.
After the 32nd rising edge, CS is pulled HIGH and a new
conversion is immediately started. This is useful in appli-
cations requiring periodic monitoring and ultralow power.
Figure 14 shows the average supply current as a function
of capacitance on CS.
It should be noticed that the external capacitor discharge
current is kept very small in order to decrease the con-
verter power dissipation in the sleep state. In the autostart
mode the analog voltage on the CS pin cannot be observed
without disturbing the converter operation using a regular
oscilloscope probe. When using this configuration, it is
important to minimize the external leakage current at the
CS pin by using a low leakage external capacitor and
properly cleaning the PCB surface.
The internal serial clock mode is selected every time the
voltage on the CS pin crosses an internal threshold volt-
age. An internal weak pull-up at the SCK pin is active while
+
–
BIT 30
SDO
SCK
CS
F
O
14
13
12
11
DATA OUTPUT
BIT 29
SIG
3-WIRE
SPI INTERFACE
C
EXT
V
CC
= 50Hz REJECTION
= EXTERNAL OSCILLATOR
= 60Hz REJECTION
BIT 0
CONVERSION
Hi-Z
2410 F11