LTC2410 Linear Technology, LTC2410 Datasheet - Page 20

• Manufacturer Part Number: LTC2410
• Description: 24-Bit No Latency ADC with Differential Input and Differential Reference
• Manufacturer: Linear Technology

APPLICATIO S I FOR ATIO
LTC2410
velocity is approximately 183ps/inch for internal traces
and 170ps/inch for surface traces. Thus, a driver gener-
ating a control signal with a minimum transition time of
1ns must be connected to the converter pin through a
trace shorter than 2.5 inches. This problem becomes
particularly difficult when shared control lines are used
and multiple reflections may occur. The solution is to
carefully terminate all transmission lines close to their
characteristic impedance.
Parallel termination near the LTC2410 pin will eliminate
this problem but will increase the driver power dissipation.
A series resistor between 27 and 56 placed near the
driver or near the LTC2410 pin will also eliminate this
problem without additional power dissipation. The actual
resistor value depends upon the trace impedance and
connection topology.
An alternate solution is to reduce the edge rate of the
control signals. It should be noted that using very slow
edges will increase the converter power supply current
during the transition time. The multiple ground pins used
in this package configuration, as well as the differential
input and reference architecture, reduce substantially the
converter’s sensitivity to ground currents.
Particular attention must be given to the connection of the
F
conversion clock. This clock is active during the conver-
sion time and the normal mode rejection provided by the
internal digital filter is not very high at this frequency. A
normal mode signal of this frequency at the converter
reference terminals may result into DC gain and INL
errors. A normal mode signal of this frequency at the
converter input terminals may result into a DC offset error.
Such perturbations may occur due to asymmetric capaci-
tive coupling between the F
input and/or reference connection traces. An immediate
solution is to maintain maximum possible separation
between the F
nals. When the F
converter, substantial AC current is flowing in the loop
formed by the F
ground return path. Thus, perturbation signals may be
inductively coupled into the converter input and/or refer-
ence. In this situation, the user must reduce to a minimum
20
O
signal when the LTC2410 is used with an external
O
O
signal trace and the input/reference sig-
connection trace, the termination and the
O
signal is parallel terminated near the
U
U
O
signal trace and the converter
W
U
the loop area for the F
the differential input and reference connections.
Driving the Input and Reference
The input and reference pins of the LTC2410 converter are
directly connected to a network of sampling capacitors.
Depending upon the relation between the differential input
voltage and the differential reference voltage, these ca-
pacitors are switching between these four pins transfering
small amounts of charge in the process. A simplified
equivalent circuit is shown in Figure 15.
For a simple approximation, the source impedance R
driving an analog input pin (IN
considered to form, together with R
Figure 15), a first order passive network with a time
constant = (R
sample the input signal with better than 1ppm accuracy if
the sampling period is at least 14 times greater than the
input circuit time constant . The sampling process on the
four input analog pins is quasi-independent so each time
constant should be considered by itself and, under worst-
case circumstances, the errors may add.
When using the internal oscillator (F
LTC2410’s front-end switched-capacitor network is clocked
at 76800Hz corresponding to a 13 s sampling period.
Thus, for settling errors of less than 1ppm, the driving
source impedance should be chosen such that
= 920ns. When an external oscillator of frequency f
used, the sampling period is 2/f
error of less than 1ppm,
Input Current
If complete settling occurs on the input, conversion re-
sults will be unaffected by the dynamic input current. An
incomplete settling of the input signal sampling process
may result in gain and offset errors, but it will not degrade
the INL performance of the converter. Figure 15 shows the
mathematical expressions for the average bias currents
flowing through the IN
sampling charge transfers when integrated over a sub-
stantial time period (longer than 64 internal clock cycles).
S
+ R
SW
O
+
signal as well as the loop area for
) • C
and IN
EQ
0.14/f
+
, IN
. The converter is able to
–
EOSC
–
pins as a result of the
EOSC
, REF
O
= LOW or HIGH), the
and, for a settling
SW
.
+
or REF
and C
–
13 s/14
) can be
EQ
EOSC
(see
is
S