LTC2410 Linear Technology, LTC2410 Datasheet - Page 6

• Manufacturer Part Number: LTC2410
• Description: 24-Bit No Latency ADC with Differential Input and Differential Reference
• Manufacturer: Linear Technology

LTC2410
PI FU CTIO S
GND (Pins 1, 7, 8, 9, 10, 15, 16): Ground. Multiple
ground pins internally connected for optimum ground
current flow and V
these pins to a ground plane through a low impedance
connection.
V
(Pin 1) with a 10 F tantalum capacitor in parallel with
0.1 F ceramic capacitor as close to the part as possible.
REF
The voltage on these pins can have any value between GND
and V
maintained more positive than the reference negative
input, REF
IN
voltage on these pins can have any value between
GND – 0.3V and V
converter bipolar input range (V
from – 0.5 • (V
the converter produces unique overrange and underrange
output codes.
CS (Pin 11): Active LOW Digital Input. A LOW on this pin
enables the SDO digital output and wakes up the ADC.
Following each conversion the ADC automatically enters
the Sleep mode and remains in this low power state as
long as CS is HIGH. A LOW-to-HIGH transition on CS
during the Data Output transfer aborts the data transfer
and starts a new conversion.
6
CC
+
U
+
(Pin 5), IN
(Pin 2): Positive Supply Voltage. Bypass to GND
(Pin 3), REF
CC
as long as the reference positive input, REF
–
U
, by at least 0.1V.
REF
–
) to 0.5 • (V
(Pin 6): Differential Analog Input. The
–
CC
(Pin 4): Differential Reference Input.
CC
U
decoupling. Connect each one of
+ 0.3V. Within these limits the
REF
). Outside this input range
IN
= IN
+
– IN
–
) extends
+
, is
SDO (Pin 12): Three-State Digital Output. During the Data
Output period this pin is used as serial data output. When
the chip select CS is HIGH (CS = V
high impedance state. During the Conversion and Sleep
periods this pin is used as the conversion status output.
The conversion status can be observed by pulling CS LOW.
SCK (Pin 13): Bidirectional Digital Clock Pin. In Internal
Serial Clock Operation mode, SCK is used as digital output
for the internal serial interface clock during the Data
Output period. In External Serial Clock Operation mode,
SCK is used as digital input for the external serial interface
clock during the Data Output period. A weak internal pull-
up is automatically activated in Internal Serial Clock Op-
eration mode. The Serial Clock Operation mode is deter-
mined by the logic level applied to the SCK pin at power up
or during the most recent falling edge of CS.
F
controls the ADC’s notch frequencies and conversion
time. When the F
converter uses its internal oscillator and the digital filter
first null is located at 50Hz. When the F
to GND (F
and the digital filter first null is located at 60Hz. When F
is driven by an external clock signal with a frequency f
the converter uses this signal as its system clock and the
digital filter first null is located at a frequency f
O
(Pin 14): Frequency Control Pin. Digital input that
O
= OV), the converter uses its internal oscillator
O
pin is connected to V
CC
) the SDO pin is in a
O
CC
pin is connected
(F
O
EOSC
= V
CC
/2560.
), the
EOSC
O
,