LTC2401 Linear Technology, LTC2401 Datasheet - Page 6

• Manufacturer Part Number: LTC2401
• Description: 1-/2-Channel 24-Bit uPower No Latency ADC in MSOP-10
• Manufacturer: Linear Technology

APPLICATIO S I FOR ATIO
LTC2401/LTC2402
Output Data Format
The LTC2401/LTC2402 serial output data stream is 32 bits
long. The first 4 bits represent status information indicat-
ing the sign, selected channel, input range and conversion
state. The next 24 bits are the conversion result, MSB first.
The remaining 4 bits are sub LSBs beyond the 24-bit level
that may be included in averaging or discarded without
loss of resolution.
Bit 31 (first output bit) is the end of conversion (EOC)
indicator. This bit is available at the SDO pin during the
conversion and sleep states whenever the CS pin is LOW.
This bit is HIGH during the conversion and goes LOW
when the conversion is complete.
Bit 30 (second output bit) is LOW if the last conversion
was performed on CH0 and HIGH for CH1.
Bit 29 (third output bit) is the conversion result sign indi-
cator (SIG). If V
bit is LOW. The sign bit changes state during the zero
code.
Bit 28 (forth output bit) is the extended input range (EXR)
indicator. If the input is within the normal input range
0 V
normal input range, V
The function of these bits is summarized in Table 1.
6
IN
V
REF
SDO
SCK
CS
, this bit is LOW. If the input is outside the
IN
is >0, this bit is HIGH. If V
Hi-Z
U
SLEEP
IN
> V
U
BIT 31
EOC
REF
1
or V
CH0/CH1
BIT 30
IN
W
< 0, this bit is HIGH.
2
BIT 29
IN
SIG
Figure 1. Output Data Timing
U
is <0, this
3
BIT 28
EXT
4
DATA OUTPUT
BIT 27
MSB
Table 1. LTC2401/LTC2402 Status Bits
Input Range
V
0 < V
V
V
Bit 27 (fifth output bit) is the most significant bit (MSB).
Bits 27-4 are the 24-bit conversion result MSB first.
Bit 4 is the least significant bit (LSB).
Bits 3-0 are sub LSBs below the 24-bit level. Bits 3-0 may
be included in averaging or discarded without loss of
resolution.
Data is shifted out of the SDO pin under control of the serial
clock (SCK), see Figure 1. Whenever CS is HIGH, SDO
remains high impedance and any SCK clock pulses are
ignored by the internal data out shift register.
In order to shift the conversion result out of the device, CS
must first be driven LOW. EOC is seen at the SDO pin of the
device once CS is pulled LOW. EOC changes real time from
HIGH to LOW at the completion of a conversion. This
signal may be used as an interrupt for an external micro-
controller. Bit 31 (EOC) can be captured on the first rising
edge of SCK. Bit 30 is shifted out of the device on the first
IN
IN
IN
5
> V
= 0
< 0
IN
+
REF
/0
V
–
REF
27
LSB
BIT 4
Bit 31
EOC
24
28
0
0
0
0
BIT 0
32
CH0/CH1
Bit 30
0/1
0/1
0/1
0/1
CONVERSION
24012 F01
Bit 29
SIG
1/0
1
1
0
Bit 28
EXR
1
0
0
1