LTC2401 Linear Technology, LTC2401 Datasheet - Page 11

• Manufacturer Part Number: LTC2401
• Description: 1-/2-Channel 24-Bit uPower No Latency ADC in MSOP-10
• Manufacturer: Linear Technology

APPLICATIO S I FOR ATIO
for the forward and return paths (R1 = R2), the auxiliary
channel on the LTC2402 can measure this drop. These
errors are then removed with simple digital correction.
The result of the first conversion on CH0 corresponds to
an input voltage of V
second conversion (CH1) is – R1 • I
LTC2402’s input range is not limited to the supply rails, it
has underrange capabilities. The device’s input range is
– 300mV to V
results together, the voltage drop across the RTD’s leads
are cancelled and the final result is V
An Isolated, 24-Bit Data Acquisition System
The LTC1535 is useful for signal isolation. Figure 9 shows
a fully isolated, 24-bit differential input A/D converter
implemented with the LTC1535 and LTC2402. Power on
the isolated side is regulated by an LT1761-5.0 low noise,
low dropout micropower regulator. Its output is suitable
for driving bridge circuits and for ratiometric applications.
LOGIC 5V
REF
“SDO”
“SCK”
+ 300mV. Adding the two conversion
U
RTD
1
+ R1 • I
TANT
10 F
U
10V
RO
RE
DE
DI
+
V
ST1
EXCITATION.
CC1
1
Figure 9. Complete, Isolated 24-Bit Data Acquisition System
T1
ISOLATION
ST2
W
G1
BARRIER
EXCITATION.
1
RTD
G2
LTC1535
1/2 BAT54C
1/2 BAT54C
.
2
The result of the
T1 = COILTRONICS CTX02-14659
U
1
2
Note, the
= LOGIC COMMON
= FLOATING COMMON
OR SIEMENS B78304-A1477-A3
+
V
CC2
10 F
16V
TANT
1 F
A
B
Y
Z
During power-up, the LTC2402 becomes active at V
2.3V, while the isolated side of the LTC1535 must wait for
V
Below 4.2V, the LTC1535’s driver outputs Y and Z are in a
high impedance state, allowing the 1k
define the logic state at SCK. When the LTC2402 first
becomes active, it samples SCK; a logic “0” provided by
the 1k pull-down invokes the external serial clock mode.
In this mode, the LTC2402 is controlled by a single clock
line from the nonisolated side of the barrier, through the
LTC1535’s driver output Y. The entire power-up sequence,
from the time power is applied to V
output has reached 5V, is approximately 1ms.
Data returns to the nonisolated side through the LTC1535’s
receiver at RO. An internal divider on receiver input B sets
a logic threshold of approximately 3.4V at input A, facili-
tating communications with the LTC2402’s SDO output
without the need for any external components.
IN
SHDN
CC2
LT1761-5
+
GND
to reach its undervoltage lockout threshold of 4.2V.
2
2
2
1k
OUT
BYP
10 F
10V
TANT
2
10 F
F
SCK
SDO
CS
GND
O
LTC2402
+
ZS
FS
CH1
CH0
V
SET
SET
10 F
10V
TANT
CC
LTC2401/LTC2402
CERAMIC
10 F
CC1
2
until the LT1761’s
24012 F09
pull-down to
11
CC
=