LTC1289 Linear Technology, LTC1289 Datasheet - Page 18

• Manufacturer Part Number: LTC1289
• Description: 3 Volt Single Chip 12-Bit Data Acquisition System
• Manufacturer: Linear Technology

LTC1289
A
settling can be extended by using a slower ACLK fre-
quency. At the maximum ACLK rate of 2MHz, R
200 and C2 < 20pF will provide adequate settling.
Input Op Amps
When driving the analog inputs with an op amp it is
important that the op amp settle within the allowed time
(see Figure 10). Again, the “+” and “–” input sampling
times can be extended as described above to accommo-
date slower op amps. For single supply low voltage
applications the LT1006, LT1013 and LT1014 can be
made to settle well even with the minimum settling win-
dows of 4 s (“+” input) and 2 s (“–” input) which occur
at the maximum clock rates (ACLK = 2MHz and SCLK =
1MHz). Figures 11 and 12 show examples of adequate and
poor op amp settling. The LT1077, LT1078 or LT1079 can
be used here to reduce power consumption. Placing an RC
network at the output of the op amps will improve the
settling response and also reduce the broadband noise.
RC Input Filtering
It is possible to filter the inputs with an RC network as
shown in Figure 13. For large values of C
capacitive input switching currents are averaged into a net
DC current. Therefore, a filter should be chosen with a
small resistor and large capacitor to prevent DC drops
across the resistor. The magnitude of the DC current is
approximately I
proportional to V
time of 40 s, the input current equals 6.3 A at V
In this case, a filter resistor of 10 will cause 0.1LSB of
full-scale error. If a larger filter resistor must be used,
errors can be eliminated by increasing the cycle time as
shown in the typical curve of Maximum Filter Resistor vs
Cycle Time.
Input Leakage Current
Input leakage currents can also create errors if the source
resistance gets too large. For instance, the maximum input
leakage specification of 1 A (at 85 C) flowing through a
source resistance of 1k will cause a voltage drop of 1mV
or 1.6LSB with V
reduced at lower temperatures because leakage drops
18
PPLICATI
DC
O
IN
REF
. When running at the minimum cycle
= 100pF
U
S
= 2.5V. This error will be much
I FOR ATIO
U
V
IN
/t
W
CYC
F
and is roughly
(e.g., 1 F), the
SOURCE
IN
U
= 2.5V.
–
<
rapidly (see typical curve of Input Channel Leakage Cur-
rent vs Temperature).
Noise Coupling Into Inputs
High source resistance input signals (>500 ) are more
sensitive to coupling from external sources. It is prefer-
able to use channels near the center of the package (i.e.,
CH2-CH7) for signals which have the highest output
resistance because they are essentially shielded by the
Figure 11. Adequate Settling of Op Amps Driving Analog Input
Figure 12. Poor Op Amp Settling Can Cause A/D Errors
V
IN
Figure 13. RC Input Filtering
R
FILTER
HORIZONTAL: 500ns/DIV
HORIZONTAL: 20 s/DIV
I
IDC
C
FILTER
“+”
“–”
LTC1289
LTC1289 AIF13