LTC1289 Linear Technology, LTC1289 Datasheet - Page 17

• Manufacturer Part Number: LTC1289
• Description: 3 Volt Single Chip 12-Bit Data Acquisition System
• Manufacturer: Linear Technology

3. Analog Inputs
Because of the capacitive redistribution A/D conversion
techniques used, the analog inputs of the LTC1289 have
capacitive switching input current spikes. These current
spikes settle quickly and do not cause a problem. How-
ever, if large source resistances are used or if slow settling
op amps drive the inputs, care must be taken to insure that
the transients caused by the current spikes settle com-
pletely before the conversion begins.
Source Resistance
The analog inputs of the LTC1289 look like a 100pF
capacitor (C
shown in Figure 9. This value for R
With larger supply voltages R
example with V
500 . C
” inputs once during each conversion cycle. Large external
source resistors and capacitances will slow the settling of
A
PPLICATI
V
V
“+” INPUT
“–” INPUT
IN
IN
+
–
SCLK
ACLK
IN
CS
Figure 9. Analog Input Equivalent Circuit
R
R
gets switched between the selected “+” and “–
SOURCE
SOURCE
IN
) is series with a 1500 resistor (R
CC
+
–
O
1
= 2.7V and V
U
C1
INPUT
INPUT
C2
“–”
S
“+”
MUX ADDRESS
SHIFTED IN
2
I FOR ATIO
U
ON
3
–
= – 2.7V R
4TH SCLK
LAST SCLK
will be reduced. For
ON
W
R
Figure 10. “+” and “–” Input Settling Windows
ON
SAMPLE
4
is for V
= 1.5k
ON
LTC1289
DURING THIS TIME
C
100pF
LTC1289 AIF09
• • •
• • •
• • •
CC
IN
MUST SETTLE
becomes
U
=
“+” INPUT
= 2.7V.
t
SMPL
ON
) as
HOLD
“–” INPUT MUST SETTLE
the inputs. It is important that the overall RC time con-
stants be short enough to allow the analog inputs to
completely settle within the allotted time.
“+” Input Settling
This input capacitor is switched onto the “+” input during
the sample phase (t
phase starts at the 4th SCLK cycle and lasts until the falling
edge of the last SCLK (the 8th, 12th or 16th SCLK cycle
depending on the selected word length). The voltage on
the “+” input must settle completely within this sample
time. Minimizing R
settling time. If large “+” input source resistance must be
used, the sample time can be increased by using a slower
SCLK frequency or selecting a longer word length. With
the minimum possible sample time of 4 s, R
and C1 < 20pF will provide adequate settling.
“–” Input Settling
At the end of the sample phase the input capacitor switches
to the “–” input and the conversion starts (see Figure 10).
During the conversion, the “+” input voltage is effectively
“held” by the sample and hold and will not affect the
conversion result. However, it is critical that the “–” input
voltage be free of noise and settle completely during the
first four ACLK cycles of the conversion time. Minimizing
R
input source resistance must be used, the time allowed for
DURING THIS TIME
SOURCE
1
1ST BIT TEST
LAST SCLK (8TH, 12TH OR 16TH DEPENDING ON WORK LENGTH)
2
–
3
and C2 will improve settling time. If large “–”
4
SOURCE
SMPL
+
, see Figure 10). The sample
and C1 will improve the input
• • •
LTC1289
SOURCE
1289 AIF10
17
+
< 2k