LTC1289 Linear Technology, LTC1289 Datasheet - Page 15

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LTC1289

Manufacturer Part Number
LTC1289
Description
3 Volt Single Chip 12-Bit Data Acquisition System
Manufacturer
Linear Technology
Datasheet

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Logic Levels
The logic level standards for this supply range have not been
well defined. What standards that do exist are not universally
accepted. The trip point on the logic inputs of the LTC1289 is
0.28 V
type logic levels and processors that are specified at 3.3V.
The output D
dards. The following summarizes such levels.
The LTC1289 can be driven with 5V logic even when V
is at 3.3V. This is due to a unique input protection device
that is found on the LTC1289.
Microprocessor Interfaces
The LTC1289 can interface directly (without external hard-
ware) to most popular microprocessor (MPU) synchro-
nous serial formats. If an MPU without a serial interface is
used, then four of the MPU’s parallel port lines can be
programmed to form the serial link to the LTC1289. Many
of the popular MPU's can operate with 3V supplies. For
example the MC68HC11 is an MPU with a serial format
(SPI). Likewise parallel MPU’s that have the 8051 type
architecture are also capable of operating at this voltage
A
PPLICATI
V
V
CC
OH
OL
. This makes the logic inputs compatible with HC
(no load)
(no load)
V
V
V
V
OUT
OH
OL
IH
IL
O
is also compatible with the above stan-
U
S
I FOR ATIO
U
Figure 5. Several LTC1289s Sharing One 3-Wire Serial Interface
OUTPUT PORT
2
V
W
0.9 V
0.1 V
0.7 V
0.2 V
SERIAL DATA
CC
MPU
0.1V
1
- 0.1V
0
CC
CC
CC
CC
U
3
3
8 CHANNELS
LTC1289
CC
CS
range. The code for these processors remains the same
and can be found in the LTC1290 datasheet or application
notes AN36A and AN36B.
Sharing the Serial Interface
The LTC1289 can share 3-wire serial interface with other
peripheral components or other LTC1289s (See Figure 5).
In this case, the CS signals decide which LTC1289 is being
addressed by the MPU.
ANALOG CONSIDERATIONS
1. Grounding
The LTC1289 should be used with an analog ground plane
and single point grounding techniques.
Pin 11 (AGND) should be tied directly to this ground plane.
Pin 10 (DGND) can also be tied directly to this ground
plane because minimal digital noise is generated within
the chip itself.
Pin 20 (V
22 F tantalum with leads as short as possible. Pin 12 (V
should be bypassed with a 0.1 F ceramic disk. For single
supply applications, V
It is also recommended that pin 13 (REF
be tied directly to the ground plane. All analog inputs should
be referenced directly to the single point ground. Digital
inputs and outputs should be shielded from and/or routed
away from the reference and analog circuitry.
3
8 CHANNELS
LTC1289
CS
CC
) should be bypassed to the ground plane with a
3
8 CHANNELS
LTC1289
CS
can be tied to the ground plane.
3-WIRE SERIAL
INTERFACE TO OTHER
PERIPHERALS OR LTC1289s
LTC1289 AIF05
) and pin 9 (COM)
LTC1289
15
)

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