AD5292 Analog Devices, AD5292 Datasheet - Page 7

• Manufacturer Part Number: AD5292
• Description: (AD5291 / AD5292) Digital Potentiometer
• Manufacturer: Analog Devices

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INTERFACE TIMING SPECIFICATIONS
V
Table 5.
Parameter
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
1
2
3
4
5
1
2
3
4
5
6
7
8
9
10
11 4
12 4
12 4
12 4
12 4
13 4
13 4
14 4
RESET
POWER-UP
All input signals are specified with t
Maximum SCLK frequency is 50 MHz.
Refer to t
R
Typical power supply voltage slew rate of 2 ms/V.
2
DD
PULL_UP
4
/V
SS
= 2.2 kΩ to V
5
= ±15 V, V
12
and t
13
for RDAC register and memory commands operations.
LOGIC
LOGIC
Limit
20
10
10
10
5
5
1
400
14
1
40
2.4
410
8
1.5
450
1.3
450
20
2
, with a capacitance load of 168 pF.
3
= 2.7 V to 5.5 V, −40°C < T
0
1
R
0
= t
F
= 1 ns/V (10% to 90% of V
Unit
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns max
μs max
ns max
ms max
ms min
ns max
ms max
ns max
ns min
ms max
C3
CONTROL BITS
C2
C1
Figure 2. AD5291/AD5292 Shift Register Content
Description
SCLK cycle time
SCLK high time
SCLK low time
SYNC to SCLK falling edge setup time
Data setup time
Data hold time
SCLK falling edge to SYNC rising edge
Minimum SYNC high time
SYNC rising edge to next SCLK fall ignore
RDY rising edge to SYNC falling edge
SYNC rising edge to RDY fall time
RDY low time, RDAC register write command execute time (R-Perf mode)
RDY low time, RDAC register write command execute time (normal mode)
RDY low time, memory program execute time
Software\hardware reset
RDY low time, RDAC register readback execute time
RDY low time, memory readback execute time
SCLK rising edge to SDO valid
Minimum RESET pulse width (asynchronous)
Power-on OTP restore time
A
C0
< + 105°C. All specifications T
DD
DB9 (MSB)
) and timed from a voltage level of (V
D9
Rev. 0 | Page 7 of 28
D8
D7
D6
DATA BITS
D5
MIN
D4
to T
IL
+ V
MAX
IH
D3
)/2.
, unless otherwise noted.
D2
D1
DB0 (LSB)
D0
AD5291/AD5292