AD5292 Analog Devices, AD5292 Datasheet - Page 21

• Manufacturer Part Number: AD5292
• Description: (AD5291 / AD5292) Digital Potentiometer
• Manufacturer: Analog Devices

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SHUTDOWN MODE
The AD5291/AD5292 can be placed in shutdown mode by
executing the software shutdown command, Command 8 (see
Table 9), and setting the LSB, D0, to 1. This feature places the
RDAC in a special state in which Terminal A is open-circuited and
Wiper W is connected to Terminal B. The contents of the
RDAC register are unchanged by entering shutdown mode.
However, all commands listed in Table 9 are supported while in
shutdown mode. Execute Command 8 (see Table 9) and set the
LSB, D0, to 0 to exit shutdown mode.
RESISTOR PERFORMANCE MODE
This mode activates a new, patented 1% end-to-end resistor
tolerance that ensures a ±1% resistor tolerance on each code,
that is, code = half scale, R
(AD5291) or Table 4 (AD5292) to check which codes achieve
±1% resistor tolerance. The resistor performance mode is
activated by programming Bit C2 of the control register (see
Table 11 and Table 12). The typical settling time is shown in
Figure 31.
RESET
A low-to-high transition of the hardware RESET pin loads the
RDAC register with the contents of the most recently programmed
20-TP memory location. The AD5291/AD5292 can also be reset
through software by executing Command 4 (see Table 9). If no
20-TP memory location is programmed, then the RDAC register
loads with midscale upon reset. The control register is restored
with default bit settings; see Table 12.
DAISY-CHAIN OPERATION
The shift register serial data output pin (SDO) serves two
purposes. It can be used to read the contents of the wiper
setting or the internal memory values using Command 2 and
Command 5, respectively (see Table 9) or it can be used to
daisy-chain multiple devices. The remaining instructions are valid
for daisy-chaining multiple devices in simultaneous operations.
Daisy-chaining minimizes the number of port pins required
from the controlling IC (see Figure 43). The SDO pin contains
an open-drain N-Channel FET that requires a pull-up resistor,
if this function is used. As shown in Figure 43, users must tie
the SDO pin of one package to the DIN pin of the next package.
Users may need to increase the clock period, because the pull-
up resistor and the capacitive loading at the SDO/DIN interface
may require additional time delay between subsequent devices.
When two AD5291/AD5292 devices are daisy-chained, 32 bits
of data are required. The first 16 bits go to U2, and the second
16 bits go to U1. Hold the SYNC pin low until all 32 bits are
clocked into their respective shift registers. The SYNC pin is
then pulled high to complete the operation.
WB
= 10 kΩ ± 100 Ω. See Table 2
Rev. 0 | Page 21 of 28
RDAC ARCHITECTURE
To achieve optimum cost performance, Analog Devices has
patented the RDAC segmentation architecture for all the digital
potentiometers. In particular, the AD5291/AD5292 employ a
three-stage segmentation approach, as shown in Figure 44. The
AD5291/AD5292 wiper switch is designed with the transmission
gate CMOS topology and with the gate voltages derived from
V
PROGRAMMING THE VARIABLE RESISTOR
Rheostat Operation—1% Resistor Tolerance
The AD5291/AD5292 operate in rheostat mode when only two
terminals are used as a variable resistor. The unused terminal
can be left floating or tied to the W terminal, as shown in Figure 45.
The nominal resistance between Terminal A and Terminal B,
R
accessed by the wiper terminal. The 8-/10-bit data in the RDAC
latch is decoded to select one of the 256/1024 possible wiper
AB
DD
SCLK
CONTROLLER
ADDRESS
DECODER
, is available in 20 kΩ and has 256 or 1024 tap points
8-/10-BIT
and V
MICRO-
MOSI
SS
Figure 44. AD5291/AD5292 Simplified RDAC Circuit
SS
Figure 43. Daisy-Chain Configuration Using SDO
.
A
B
Figure 45. Rheostat Mode Configuration
DIN
W
SYNC
A
B
AD5291/
AD5292
U1
SCLK
SDO
A
B
R
R
R
R
L
L
L
L
V
W
LOGIC
R
2.2kΩ
P
AD5291/AD5292
R
R
R
R
A
B
M
M
M
M
DIN
R
R
SYNC
W
W
AD5291/
AD5292
W
U2
S
W
SCLK
SDO
W