AD5292 Analog Devices, AD5292 Datasheet - Page 22

• Manufacturer Part Number: AD5292
• Description: (AD5291 / AD5292) Digital Potentiometer
• Manufacturer: Analog Devices

www.DataSheet4U.com
AD5291/AD5292
settings. The AD5291/AD5292 contain an internal ±1% resistor
performance mode that can be disabled or enabled (this is
enabled by default), by programming Bit C2 of the control
register (see Table 11 and Table 12). The digitally programmed
output resistance between the W terminal and the A terminal,
R
nally calibrated to give a maximum of ±1% absolute resistance
error across a wide code range. As a result, the general equations
for determining the digitally programmed output resistance
between the W terminal and B terminal are
AD5291:
AD5292:
where:
D is the decimal equivalent of the binary code loaded in the
8-/10-bit RDAC register.
R
Similar to the mechanical potentiometer, the resistance of the
RDAC between the W terminal and the A terminal also produces a
digitally controlled complementary resistance, R
calibrated to give a maximum of 1% absolute resistance error.
R
data loaded into the latch increases. The general equations for
this operation are
AD5291:
AD5292:
where:
D is the decimal equivalent of the binary code loaded in the
8-/10-bit RDAC register.
R
In the zero-scale condition, a finite total wiper resistance of 120 Ω
is present. Regardless of which setting the part is operating in,
take care to limit the current between Terminal A and Terminal B,
between Terminal W and Terminal A, and between Terminal W
and Terminal B, to the maximum continuous current of ±3 mA or
to the pulse current specified in Table 6. Otherwise, degradation
or possible destruction of the internal resistors may occur.
PROGRAMMING THE POTENTIOMETER DIVIDER
Voltage Output Operation
The digital potentiometer easily generates a voltage divider at
the wiper to B and at the wiper to A that is proportional to the
input voltage at A to B, as shown in Figure 46. Unlike the polarity
WA
AB
WA
AB
, and between the W terminal and B terminal, R
is the end-to-end resistance.
is the end-to-end resistance.
starts at the maximum resistance value and decreases as the
R
R
R
R
WB
WB
WA
WA
(
(
(
(
D
D
D
D
)
)
)
)




1024
256
256
1024
D
D
1024
256




R
D
R
D
AB

AB

R
R
AB
AB
WA
. R
WB
WA
, is inter-
is also
Rev. 0 | Page 22 of 28
(1)
(2)
(3)
(4)
of V
W to A, and W to B can be at either polarity.
If ignoring the effect of the wiper resistance for simplicity, con-
necting the A terminal to 30 V and the B terminal to ground
produces an output voltage at the Wiper W to Terminal B
ranging from 0 V to 1 LSB less than 30 V. Each LSB of voltage is
equal to the voltage applied across Terminal A and Terminal B,
divided by the 256/1024 positions of the potentiometer divider.
The general equations defining the output voltage at V
respect to ground for any valid input voltage applied to Terminal A
and Terminal B are
AD5291:
AD5292:
If using the AD5291/AD5292 in voltage divider mode as in
Figure 46, then the ±1% resistor tolerance calibration feature
reduces the error when matching with discrete resistors. However,
it is recommended to disable the internal ±1% resistor tolerance
calibration feature by programming Bit C2 of the control
register (see Table 11 and Table 12) to optimize wiper position
update rate. In this configuration, the RDAC is ratiometric and
resistor tolerance error does not affect performance.
Operation of the digital potentiometer in the voltage divider
mode results in a more accurate operation over temperature.
Unlike the rheostat mode, the output voltage is dependent
mainly on the ratio of the internal resistors, R
not the absolute values. Therefore, the temperature drift reduces
to 5 ppm/°C.
EXT_CAP CAPACITOR
A 1 μF capacitor to GND must be connected to the EXT_CAP
pin (see Figure 47) on power-up and throughout the operation
of the AD5291/AD5292.
DD
V
V
W
W
to GND, which must be positive, voltage across A to B,
(
(
D
D
)
)


Figure 46. Potentiometer Mode Configuration
Figure 47. Hardware Setup for EXT_CAP Pin
256
1024
D
D
EXT_CAP

1µF
C1

V
V
A
V
A
IN


256
1024
256
1024
A
B

AD5291/
AD5292

D
MEMORY
BLOCK
W
GND
D
OTP


V
V
V
B
OUT
B
WA
and R
WB
W
with
, and
(5)
(6)