AD5292 Analog Devices, AD5292 Datasheet - Page 10

• Manufacturer Part Number: AD5292
• Description: (AD5291 / AD5292) Digital Potentiometer
• Manufacturer: Analog Devices

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AD5291/AD5292
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Table 8. Pin Function Descriptions
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
Mnemonic
RESET
V
A
W
B
V
EXT_CAP
V
GND
DIN
SCLK
SYNC
SDO
RDY
SS
DD
LOGIC
Hardware Reset Pin. Refreshes the RDAC register with the contents of the 20-TP memory register. Factory
logic high transition. Tie RESET to V
Negative Supply. Connect to 0 V for single-supply applications. This pin should be decoupled with 0.1 μF
ceramic capacitors and 10 μF capacitors.
Terminal A of RDAC. V
Wiper Terminal of RDAC. V
Terminal B of RDAC. V
Positive Power Supply. This pin should be decoupled with 0.1 μF ceramic capacitors and 10 μF capacitors.
External Capacitor. Connect a 1 μF capacitor to EXT_CAP. This capacitor must have a voltage rating of ≥7 V.
Logic Power Supply; 2.7 V to 5.5 V. This pin should be decoupled with 0.1 μF ceramic capacitors and 10 μF
capacitors.
Serial Data Input. The AD5291/AD5292 have a 16-bit shift register. Data is clocked into the register on the falling
edge of the serial clock input.
Serial Clock Input. Data is clocked into the shift register on the falling edge of the serial clock input. Data can be
transferred at rates up to 50 MHz.
Falling Edge Synchronization Signal. This is the frame synchronization signal for the input data. When SYNC
goes low, it enables the shift register and data is transferred in on the falling edges of the following clocks. The
selected register is updated on the rising edge of SYNC following the 16
before the 16
the DAC.
Serial Data Output. This open-drain output requires an external pull-up resistor. SDO can be used to clock data
from the shift register in daisy-chain mode or in readback mode.
Ready Pin. This active-high open-drain output identifies the completion of a write or read operation to or from
the RDAC register or memory.
Description
default loads midscale until the first 20-TP wiper memory location is programmed. RESET is activated at the
Ground Pin, Logic Ground Reference.
th
clock cycle, the rising edge of SYNC acts as an interrupt, and the write sequence is ignored by
SS
SS
≤ V
≤ V
EXT_CAP
SS
B
A
RESET
≤ V
≤ V
≤ V
V
V
Figure 5. Pin Configuration
DD
SS
W
W
DD
A
B
DD
≤ V
.
Rev. 0 | Page 10 of 28
.
1
2
3
4
5
6
7
LOGIC
DD
Not to Scale
AD5291/
AD5292
TOP VIEW
.
if not used.
14
13
12
11
10
9
8
RDY
SDO
SYNC
SCLK
DIN
GND
V
LOGIC
th
clock cycle. If SYNC is taken high