AD9219BCPZRL-65 Analog Devices, Inc., AD9219BCPZRL-65 Datasheet - Page 25

• Manufacturer Part Number: AD9219BCPZRL-65
• Description: Quad, 10-bit, 40/65 Msps Serial Lvds 1.8 V A/d Converter
• Manufacturer: Analog Devices, Inc.

Two output clocks are provided to assist in capturing data from
the AD9219. The DCO is used to clock the output data and is
equal to six times the sampling clock (CLK) rate. Data is
clocked out of the AD9219 and must be captured on the rising
and falling edges of the DCO that supports double data rate
Table 9. Flex Output Test Modes
Output Test
Mode Bit
Sequence
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1
PN, or pseudorandom number, sequence is determined by the number of bits in the shift register. The long sequence is 23 bits and the short sequence is
9 bits. How the sequence is generated and utilized is described in the ITU O.150 standard. In general, the polynomial, X23 + X18 + 1 (long) and X9 + X5 + 1
(short), defines the pseudorandom sequence.
Pattern Name
OFF (default)
Midscale Short
+Full-Scale Short
−Full-Scale Short
Checker Board
PN Sequence Long
PN Sequence Short
One/Zero Word Toggle
User Input
One/Zero Bit Toggle
1× Sync
One Bit High
Mixed Frequency
1
1
Digital Output Word 1
N/A
1000 0000 (8 bit)
10 0000 0000 (10 bit)
1000 0000 0000 (12 bit)
10 0000 0000 0000 (14 bit)
1111 1111 (8 bit)
11 1111 1111 (10 bit)
1111 1111 1111 (12 bit)
11 1111 1111 1111 (14 bit)
0000 0000 (8 bit)
00 0000 0000 (10 bit)
0000 0000 0000 (12 bit)
00 0000 0000 0000 (14 bit)
1010 1010 (8 bit)
10 1010 1010 (10 bit)
1010 1010 1010 (12 bit)
10 1010 1010 1010 (14 bit)
N/A
N/A
1111 1111 (8 bit)
11 1111 1111 (10 bit)
1111 1111 1111 (12 bit)
11 1111 1111 1111 (14 bit)
Register 0x19 to Register 0x1A
1010 1010 (8 bit)
10 1010 1010 (10 bit)
1010 1010 1010 (12 bit)
10 1010 1010 1010 (14 bit)
0000 1111 (8 bit)
00 0001 1111 (10 bit)
0000 0011 1111 (12 bit)
00 0000 0111 1111 (14 bit)
1000 0000 (8 bit)
10 0000 0000 (10 bit)
1000 0000 0000 (12 bit)
10 0000 0000 0000 (14 bit)
1010 0011 (8 bit)
10 0110 0011 (10 bit)
1010 0011 0011 (12 bit)
10 1000 0110 0111 (14 bit)
Rev. 0 | Page 25 of 52
(DDR) capturing. The frame clock out (FCO) is used to signal
the start of a new output byte and is equal to the sampling clock
rate. See the timing diagram shown in Figure 2 for more
information.
Digital Output Word 2
N/A
Same
Same
Same
0101 0101 (8 bit)
01 0101 0101 (10 bit)
0101 0101 0101 (12 bit)
01 0101 0101 0101 (14 bit)
N/A
N/A
0000 0000 (8 bit)
00 0000 0000 (10 bit)
0000 0000 0000 (12 bit)
00 0000 0000 0000 (14 bit)
Register 0x1B to Register 0x1C
N/A
N/A
N/A
N/A
AD9219
Subject
to Data
Format
Select
N/A
Yes
Yes
Yes
No
Yes
Yes
No
No
No
No
No
No