AD9219BCPZRL-65 Analog Devices, Inc., AD9219BCPZRL-65 Datasheet - Page 20

• Manufacturer Part Number: AD9219BCPZRL-65
• Description: Quad, 10-bit, 40/65 Msps Serial Lvds 1.8 V A/d Converter
• Manufacturer: Analog Devices, Inc.

AD9219
For best dynamic performance, the source impedances driving
VIN+ and VIN− should be matched such that common-mode
settling errors are symmetrical. These errors are reduced by the
common-mode rejection of the ADC. An internal reference
buffer creates the positive and negative reference voltages, REFT
and REFB, respectively, that define the span of the ADC core.
The output common-mode of the reference buffer is set to
midsupply, and the REFT and REFB voltages and span are
defined as
It can be seen from these equations that the REFT and REFB
voltages are symmetrical about the midsupply voltage and, by
definition, the input span is twice the value of the VREF voltage.
Maximum SNR performance is always achieved by setting the
ADC to the largest span in a differential configuration. In the
case of the AD9219, the largest input span available is 2 V p-p.
Differential Input Configurations
There are several ways in which to drive the AD9219 either
actively or passively. In either case, the optimum performance is
achieved by driving the analog input differentially. One example
is by using the
performance and a flexible interface to the ADC (see Figure 49)
for baseband applications. This configuration is common for
medical ultrasound systems.
However, the noise performance of most amplifiers is not
adequate to achieve the true performance of the AD9219. For
applications where SNR is a key parameter, differential transfor-
mer coupling is the recommended input configuration. Two
examples are shown in Figure 46 and Figure 47.
In any configuration, the value of the shunt capacitor, C, is
dependent on the input frequency and may need to be reduced
or removed.
REFT = 1/2 (AVDD + VREF)
REFB = 1/2 (AVDD − VREF)
Span = 2 × (REFT − REFB) = 2 × VREF
1V p-p
AD8332
0.1 F
differential driver. It provides excellent
120nH
0.1 F
22pF
18nF
INH
LMD
Figure 49. Differential Input Configuration Using the
274
LNA
LOP
LON
AD8332
0.1 F
0.1 F
Rev. 0 | Page 20 of 52
VIP
VIN
VGA
VOH
VOL
2V p-p
Figure 47. Differential Transformer Coupled Configuration for IF Applications
Single-Ended Input Configuration
A single-ended input may provide adequate performance in
cost-sensitive applications. In this configuration, SFDR and
distortion performance degrade due to the large input common-
mode swing. If the application requires a single-ended input
configuration, ensure that the source impedances on each input
are well matched in order to achieve the best possible performance.
A full-scale input of 2 V p-p can still be applied to the ADC’s VIN+
pin while the VIN− pin is terminated. Figure 48 details a typical
single-ended input configuration.
2V p-p
2V p-p
187
65
187
374
16nH
Figure 46. Differential Transformer Coupled Configuration
1k
1k
49.9
AVDD
49.9
0.1 F
0.1 F
0.1 F
1k
1k
Figure 48. Single-Ended Input Configuration
AD8332
1.0k
1.0k
0.1µF
0.1 F
AVDD
ADT1–1WT
1:1 Z RATIO
ADT1–1WT
1:1 Z RATIO
AVDD
0.1µF
for Baseband Applications
0.1 F
1k 25
1k
R
R
C
0.1 F
1k
499
10 F
AVDD
16nH
16nH
*C
*C
*C
*C
R
R
DIFF
DIFF IS OPTIONAL
DIFF
R
DIFF IS OPTIONAL
2.2pF
33
33
R
C
C
C
C
VIN–
VIN+
AD9219
ADC
1k
VREF
VIN+
VIN–
VIN–
VIN+
AD9219
AD9219
ADC
ADC
AGND
VIN+
VIN–
AD9219
ADC