AD9887A Analog Devices, Inc., AD9887A Datasheet - Page 41

• Manufacturer Part Number: AD9887A
• Description: Dual Interface For Flat Panel Displays
• Manufacturer: Analog Devices, Inc.

0x11 1
Table 36. Active VSYNC Results
Bit 5 (VSYNC Detect)
0
1
X
1
2
3
0x12 7
Table 37. Active Interface Override Settings
AIO
0
1
12
Table 38. Active Interface Select Settings
AIS
0
1
0x12 5
Table 39. Active HSYNC Override Settings
Override
0
1
The override bit is Bit 3 in Register 0x12.
AVS = 0 means VSYNC input.
AVS = 1 means sync separator.
Set this bit (Bit 3 in Register 0x11) to Logic 1 to override
the automatic interface selection. When overriding the
automatic interface selection, the active interface is set
via Bit 6 in this register.
This bit is used under two conditions. It is used to select
the active interface when the override bit (Bit 7) is set.
Alternately, it is used to determine the active interface
when the override bit is not set, but both interfaces are
detected.
This bit is used to override the automatic HSYNC selection
(Bit 2 in Register 0x11). To initiate, set this bit to Logic 1.
When overriding the automatic HSYNC selection, the
active HSYNC is set via Bit 4 in this register.
This bit determines which VSYNC to use for the analog
interface, the VSYNC input or the sync separator output.
If both VSYNC and composite SOG are detected, VSYNC
is selected. The user can override this function via Bit 3
in Register 0x12. If the override bit is set to Logic 1, this
bit is forced to the set state of Bit 2 in Register 0x12.
The default for this register is 0.
6
The default for this register is 0.
The default for this register is 0.
Result
Autodetermines the active interface
Override, Bit 6 determines the active interface
Result
Autodetermines the active interface
Override, Bit 4 determines the active interface
Active VSYNC (AVS)
Active Interface Override (AIO)
Active Interface Select (AIS)
Active HSYNC Override
Result
Analog interface
Digital interface
Override
0
0
1
1
AVS
0
1
Bit 2 in Register 0x12
2, 3
Rev. B | Page 41 of 52
0x12 4
Table 40. Active Hsync Select Settings
Select
0
1
0x12 3
Table 41. Active VSYNC Override Settings
Override
0
1
0x12 2
Table 42. Active VSYNC Select Settings
Select
0
1
0x12 1
Table 43. Coast Select Settings
Select
0
1
This bit is used under two conditions. It is used to select
the active Hsync when the override bit (Bit 5) is set.
Alternately, it is used to determine the active Hsync
when the override bit is not set, but both Hsyncs are
detected.
This bit is used to override the automatic Vsync selection
(Bit 1 in Register 0x11). To initiate this, set this bit to
Logic 1. When overriding the automatic Vsync selection,
the active interface is set via Bit 2 in this register.
This bit is used to select the active Vsync when the
override bit (Bit 3) is set.
This bit is used to select which coast source is active, the
COAST input pin or Vsync. If Vsync is selected, users
must decide whether to use the VSYNC input pin or the
output from the sync separator (Bit 3 and Bit 2).
The default for this register is 0.
The default for this register is 0.
The default for this register is 0.
Result
Autodetermines the active Vsync
Override, Bit 2 determines the active Vsync
Active Vsync Override
Active Vsync Select
Coast Select
Active Hsync Select
Result
COAST input pin
Vsync (see above text)
Result
VSYNC input
Sync separator output
Result
HSYNC input
Sync-on-green input
AD9887A