AD9887A Analog Devices, Inc., AD9887A Datasheet - Page 32

• Manufacturer Part Number: AD9887A
• Description: Dual Interface For Flat Panel Displays
• Manufacturer: Analog Devices, Inc.

AD9887A
2-WIRE SERIAL REGISTER MAP
The AD9887A is initialized and controlled by a set of registers that determine the operating modes. An external controller is used to write
and read the control registers through the 2-line serial interface port.
Table 9. Control Register Map
Address
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x0A
0x0B
0x0C
0x0D
0x0E
0x0F
R/W
Read and
Write, or
Read Only
RO
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bits
7:0
7:0
7:4
7:2
7:3
7:0
7:0
7:0
7:0
7:1
7:1
7:1
7:3
7:0
7:0
7:0
Default
Value
01101001
1101****
1*******
*01*****
***001**
10000***
10000000
10000000
00100000
10000000
10000000
10000000
1000000*
1000000*
1000000*
1*******
*1******
**0*****
***0****
****0***
1*******
*1******
**0*****
Register Name
Chip Revision
PLL Divide Ratio
MSBs
PLL Divide Ratio
LSBs
Clock Generator
Controls
Clock Phase Adjust
Clamp Placement
Clamp Duration
Hsync Output
Pulse Width
REDGAIN
GREENGAIN
BLUEGAIN
REDOFST
GREENOFST
BLUEOFST
Mode Control 1
PLL and Clamp
Control
Rev. B | Page 32 of 52
Description
Bit 7 through Bit 4 represent functional revisions to the analog
interface. Bit 3 through Bit 0 represent nonfunctional related
revisions. Revision 0 = 0000 0000.
This register is for Bits[11:4] of the PLL divider. Larger values mean the
PLL operates at a faster rate. This register should be loaded first when
a change is needed. (This gives the PLL more time to lock.)
This register is for Bits[3:0] of the PLL divider. Links to the PLL divide
ratio MSBs to make a 12-bit value.
Bit 7—Must be set to 1 for proper device operation.
Bits[6:5]—VCO Range Select. Selects VCO frequency range (see the
PLL section).
Bits[4:2]—Charge-Pump Current. Varies the current that drives the
low-pass filter (see the PLL section).
Clock Phase Adjust. Larger values mean more delay. (1 LSB = T/32)
Places the clamp signal an integer number of clock periods after the
trailing edge of the Hsync signal.
Number of clock periods that the clamp signal is actively clamping.
Sets the number of pixel clocks that HSOUT remains active.
Controls ADC input range (contrast) of red channel. Bigger values
result in less contrast.
Controls ADC input range (contrast) of green channel. Bigger values
result in less contrast.
Controls ADC input range (contrast) of blue channel. Bigger values
result in less contrast.
Controls dc offset (brightness) of red channel. Bigger values decrease
brightness.
Controls dc offset (brightness) of green channel. Bigger values
decrease brightness.
Controls dc offset (brightness) of blue channel. Bigger values decrease
brightness.
Bit 7—Channel Mode. Determines single-channel or dual-channel output
mode. Logic 0 = single-channel mode; Logic 1 = dual-channel mode.
Bit 6—Output Mode. Determines interleaved or parallel output mode.
Logic 0 = interleaved mode; Logic 1 = parallel mode.
Bit 5—Output Port Phase (OUTPHASE). Determines which port outputs
the first data byte after Hsync. Logic 0 = B port; Logic 1 = A port.
Bit 4—HSYNC Output Polarity. Logic 0 = logic high sync; Logic 1 =
logic low sync.
Bit 3—VSYNC Output Invert. Logic 0 = invert; Logic 1 = no invert.
Bit 7—HSYNC Input Polarity. Indicates the polarity of incoming HSYNC
signal to the PLL. Logic 0 = active low; Logic 1 = active high.
Bit 6—COAST Input Polarity. Changes polarity of external coast signal.
Logic 0 = active low; Logic 1 = active high.
Bit 5—Clamp Input Signal Source (EXTCLMP). Chooses between HSYNC
for CLAMP signal and another external signal to be used for clamping.
Logic 0 = HSYNC; Logic 1 = externally provided clamp signal.
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