CY7C4265-10AC Cypress Semiconductor Corp, CY7C4265-10AC Datasheet - Page 8

IC DEEP SYNC FIFO 16KX18 64LQFP

CY7C4265-10AC

Manufacturer Part Number
CY7C4265-10AC
Description
IC DEEP SYNC FIFO 16KX18 64LQFP
Manufacturer
Cypress Semiconductor Corp
Series
CY7Cr
Datasheet

Specifications of CY7C4265-10AC

Function
Synchronous
Memory Size
288K (16K x 18)
Data Rate
100MHz
Access Time
8ns
Voltage - Supply
3.3V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
64-LQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
428-1235
Switching Waveforms
Document #: 38-06004 Rev. *A
First Data Word Latency after Reset with Simultaneous Read and Write
Reset Timing
Notes:
17. The clocks (RCLK, WCLK) can be free-running during reset.
18. After reset, the outputs will be LOW if OE = 0 and three-state if OE = 1.
19. When t
20. The first word is available the cycle after EF goes HIGH, always.
REN, WEN,
Q
D
0
0
Q
WCLK
RCLK
EF,PAE
FF,PAF,
WEN
–D
–Q
0 –
REN
t
SKEW2
OE
EF
17
17
RS
Q
HF
LD
17
. The Latency Timing applies only at the Empty Boundary (EF = LOW).
SKEW2
t
ENS
[17]
> minimum specification, t
t
DS
D
0
(FIRSTVALID WRITE)
(continued)
FRL
t
SKEW2
(maximum) = t
t
t
t
RSF
RSF
RSF
t
RS
t
OLZ
t
FRL
CLK
[19]
+ t
SKEW2
t
D
REF
. When t
1
SKEW2
t
OE
< minimum specification, t
t
RSR
t
D
A
2
FRL
(maximum) = either 2*t
D
0
t
A
[19]
D
3
CLK
OE=0
OE=1
+ t
CY7C4255
CY7C4265
SKEW2
[18]
Page 8 of 22
or t
CLK
4255–8
D
4255–9
1
+
D
4

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