MT8941BP1 Zarlink Semiconductor, Inc., MT8941BP1 Datasheet - Page 6

• Manufacturer Part Number: MT8941BP1
• Manufacturer: Zarlink Semiconductor, Inc.

Note: X: indicates don’t care
M
S
X
0
0
1
M
S
0
0
1
0
1
M
S
1
0
1
1
M
S
1
0
0
1
1
Operation
NORMAL
DIVIDE-1
DIVIDE-2
Mode of
FREE-RUN
Operation
CLOCK-1
CLOCK-2
NORMAL
Mode of
SINGLE
SINGLE
Table 1 - Major Modes of DPLL #1
Table 2 - Major Modes of DPLL #2
Zarlink Semiconductor Inc.
Provides the T1 (1.544 MHz) clock synchronized
to the falling edge of the input frame pulse (F0i).
DPLL #1 divides the CVb input by 193. The
divided output is connected to DPLL #2.
DPLL #1 divides the CVb input by 256. The
divided output is connected to DPLL #2.
Provides CEPT/ST-BUS timing signals locked
to the falling edge of the 8 kHz input signal at
C8Kb.
Provides CEPT/ST-BUS timing and framing
signals with no external inputs, except the
master clock.
Provides CEPT/ST-BUS timing signals locked
to the falling edge of the 8 kHz internal signal
provided by DPLL #1.
Provides CEPT/ST-BUS timing signals locked
to the falling edge of the 8 kHz internal signal
provided by DPLL #1.
MT8941B
6
Function
Function
Data Sheet