MT8941BP1 Zarlink Semiconductor, Inc., MT8941BP1 Datasheet - Page 22

• Manufacturer Part Number: MT8941BP1
• Manufacturer: Zarlink Semiconductor, Inc.

AC Electrical Characteristics
† Timing is over recommended temperature & power supply voltages.
‡ Typical figures are at 25
* Please review the section on "Jitter Performance and Lock-in Range".
† Timing is over recommended temperature & power supply voltages.
‡ Typical figures are at 25
AC Electrical Characteristics
1
2
3
4
5
6
Master clock
inputs
1
2
3
4
C
L
O
C
K
S
F0b input pulse width (LOW)
C4b input clock period
Frame pulse (F0b) setup time
Frame pulse (F0b) hold time
Master clocks input rise time
Master clocks input fall time
Master clock period
(12.352 MHz)*
Master clock period
(16.384MHz)*
Duty Cycle of master clocks
Lock-in Range
Characteristics
Characteristics
2.4 V
1.5 V
0.4 V
°
°
C and are for design aid only: not guaranteed and not subject to production testing.
C and are for design aid only: not guaranteed and not subject to production testing.
DPLL #1
DPLL #2
† - Voltages are with respect to ground (V
† - Voltages are with respect to ground (V
t
r
Sym.
t
t
Figure 17 - Master Clock Inputs
P12
P16
t
P12
t
Sym.
t
t
r
f
t
WFP
t
t
P4o
FH
FS
or t
Zarlink Semiconductor Inc.
P16
80.943
61.023
-2.33
-1.69
MT8941B
Min.
45
Min.
22
80.958
61.035
Typ.
Typ.
244
244
50
50
25
‡
SS
‡
SS
) unless otherwise stated.
) unless otherwise stated.
80.974
61.046
Max.
+2.33
+1.69
Max.
10
10
55
Units
Units
ns
ns
ns
ns
Hz
ns
ns
ns
ns
%
For DPLL #1, while
operating to provide the
T1 clock signal.
For DPLL #2, while
operating to provide the
CEPT and ST-BUS timing
signals.
With the Master frequency
tolerance at ±32 ppm.
(Refer to Figure 14)
(Refer to Figure 18)
Test Conditions
t
f
Test Conditions
Data Sheet