MTC-20144TQ-I AMI Semiconductor, Inc., MTC-20144TQ-I Datasheet - Page 20

• Manufacturer Part Number: MTC-20144TQ-I
• Description: Integrated ADSL CMOS Analog Front-End Circuit
• Manufacturer: AMI Semiconductor, Inc.

Receive / Transmit Interface
Timing
This interface is a triple (RX,TX, TXE)
nibble-serial interface running at 8.8
MHz sampling (normal mode). The data
are represented in 16 bits format, and
transferred in groups of 4 bits (nibbles).
The LSBs are transferred first. The MTC-
20144 generates a nibble clock (=
master clock in normal mode, CLKNIB in
OSR=2 mode) and word signals
shared by the three interfaces.
Data is transmitted on the rising edge of
the master clock (CLKM/CLKNIB) and
sampled on the low going edge of
CLKM/CLKNIB. This holds for the data
stream from MTC-20144 and from the
digital processor.
Data, CLWD setup and hold times are 5
ns with reference to the falling edge of
CLKM/CLKNIB.
RXD is sampled with CLKM rising edge.
Power Down
When pin Pdown=”1”, the chip is set
in power down mode. In this mode all
analog functional blocks are
deactivated except : preamplifiers
(TX/TXE), clock circuits for output clock
CLKM. PDown does not affect the
digital part of the chip. The chip is
activated when Pdown=”0”.
Power Down Conditions
In power down mode the following
conditions hold :
- Output voltages at TX01/TX02=AGND
- The XTAL output clock on pin CLKM
- All digital settings are retained.
- Digital output on pins RXDx don’t care
Following external conditions are added:
- Clock pins CLWD is running.
- CTRLIN signals can still be allowed.
- AGND remains at AVDD/2
- Input signals at TXDx inputs are not
( circuit is powered up )
keeps running.
( not floating ).
strobed.
Reset Function
The reset function is implied when the
RESETN pin is at a low voltage input
level.
In this condition, the reset function can
be easily used for power up reset
conditions.
Detailed Description
During reset :
- All clock outputs are deactivated and
- (except for the XTAL and masterclock
put to logical ”1”
CLKM)
’0’ (NT)
’1’ (LT)
Fig. 14: TX/TXE/RX Digital Interface Timing
RX : LNA -> HC2 -> ADC
TX : DAC -> SC2 -> TX
RX : LNA -> SC2 -> ADC
TX : DAC -> HC2 -> TX
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After reset :
- OSR = 4
- All analog gains (RX, TX, TXE) are set
- Nominal filter frequency bands
- LNA input = ”11” (max attenuation)
- VCO dac and Echo path disabled
- Depending of the LTNT pin value the
Digital outputs are placed in don’t care
condition (non-floating)
MTC-20144
to minimum value.
(138 KHz, 1.104MHz)
following configuration is choosen: